An enhanced single gate driven voltage‐balanced SiC MOSFET stack topology suitable for high‐voltage low‐power applications

Abstract

In the fabrication of some high-voltage low-power applications, low cost is much concerned, and thus using silicon carbide (SiC) MOSFET stack consisting of series connected low-voltage devices is preferred rather than using an expensive single high-voltage device. Therefore, a cost-efficient single gate driven voltage-balanced SiC MOSFET stack topology is proposed in this paper, where only some passive components are equipped with the stack. With a concept of single gate driver, the gate driver design of an SiC MOSFET stack is simplified. With an automatic balancing circuit which operates well with the sequential lagging single gate driver, good voltage balancing of SiC MOSFETs in the stack is realized without causing much extra loss and no additional active control is required. The working principle is illustrated in detail and the parameter selection together with design consideration is presented. Next, this topology is compared with RCD snubber method and active delay adjusting method to better illustrate its advantages. Finally, in a typical high-voltage low-power application, auxiliary power supply, the simulation and experimental results further verify the effectiveness of the proposed topology.

Short-Circuit Characteristic of Single Gate Driven SiC MOSFET Stack and Its Improvement With Strong Antishort Circuit Fault Capabilities

“…Only one standard GD is required; PDU in this stack consists of coupling capacitor C ai (i =1~ 4), gate resistor R gi , static voltage balancing resistor R si and Zener diodes D ai , D bi ; RCD 2 circuit and additional R g0 C a0 branch are for voltage balancing. In the previous work [24], along with detailed parameters design, it has been validated that this single gate driven stack topology performs a much lower total loss compared with conventional separated gate driven stack with RCD snubbers. In this paper, to make it 5.…”

“…To facilitate the analysis, based on the preserved single gate driven SiC MOSFET stack (n = 4) with corresponding clamping VB circuits in [24] (also shown as the stack without the improved part in the next Section III) and the key parameters described in Table I, the LTspice simulation waveforms are presented to reveal the mechanism in the SC occurrence of single gate driven stack, as shown in Fig. 3 when FUL occurs under a bus voltage VDC of 3 kV.…”