A case for neuromorphic ISAs

Hashmi, Atif; Nere, Andrew; Thomas, James Jamal; Lipasti, Mikko H.

doi:10.1145/1950365.1950385

Cited by 31 publications

(15 citation statements)

References 31 publications

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“…Hardware implementations for NNs have been developed using various forms of technology [58], including ASIC (both digital and analog) [67], [19], [41], [72], [1], FPGA [89], and neuromorphic hardware [75], [37], along with specialized fault-tolerant designs [4], [78], [36]. GPU implementations of NNs [44], [63] have also gained in popularity.…”

Section: Neural Network Implementationsmentioning

confidence: 99%

BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing

Grigorian¹,

Farahpour²,

Reinman³

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Applications with large amounts of data, real-time constraints, ultra-low power requirements, and heavy computational complexity present significant challenges for modern computing systems, and often fall within the category of high performance computing (HPC). As such, computer architects have looked to high performance single instruction multiple data (SIMD) architectures, such as accelerator-rich platforms, for handling these workloads. However, since the results of these applications do not always require exact precision, approximate computing may also be leveraged. In this work, we introduce BRAINIAC, a heterogeneous platform that combines precise accelerators with neural-network-based approximate accelerators. These reconfigurable accelerators are leveraged in a multi-stage flow that begins with simple approximations and resorts to more complex ones as needed. We employ high-level, applicationspecific light-weight checks (LWCs) to throttle this multi-stage acceleration flow and reliably ensure user-specified accuracy at runtime. Evaluation of the performance and energy of our heterogeneous platform for error tolerance thresholds of 5%-25% demonstrates an average of 3× gain over computation that only includes precise acceleration, and 15×-35× gain over softwarebased computation.

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Section: Neural Network Implementationsmentioning

confidence: 99%

BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing

Grigorian¹,

Farahpour²,

Reinman³

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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“…Understanding the computational principles of these interactions is essential for developing novel computing frameworks. Recent progresses in understanding the principles of neural information processing and at the same time the desire to build new computing systems, has led researchers to develop neuromorphic architectures that map the brain computational principles on hardware by means of the mixed-mode analog/digital circuits [1][2][3][4]. To date, neuromorphic hardware comprises many different building blocks such as spiking neurons [5], synapses [6,7], plastic mechanisms [5,[8][9][10], photoreceptors [11,12], auditory cells [13], etc.…”

Section: Introductionmentioning

confidence: 99%

An analog astrocyte–neuron interaction circuit for neuromorphic applications

Ranjbar

Amiri

2015

J Comput Electron

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Recent neurophysiologic findings have shown that astrocytes (the most abundant type of glial cells) are active partners in neural information processing and regulate the synaptic transmission dynamically. Motivated by these findings, in the present research, an analog neuromorphic circuit to study neuron-astrocyte signaling is presented. In this analog circuit, the firing dynamics of the neuron is described by Izhikevich neuron circuit and the Ca 2+ dynamics of a single astrocyte explained by a functional simplified model introduced by Montaseri et al. Using the proposed neuronastrocyte circuit, it is demonstrated that the proposed analog astrocyte is able to activate the analog neuron or change the neuron spiking frequency through bidirectional communication. This suggests that analog astrocyte is capable of modulating spike transmission frequency. Moreover, our results suggest that the analog circuit of neuron-astrocyte crosstalk produces diverse neural responses and therefore enhances the information processing capabilities of the neuromorphic circuits. This is suitable for applications in reconfigurable neuromorphic devices which implement biologically brain circuits.

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“…Silicon allows us to bypass these biological details and compute data at a higher abstraction without concern of the molecular level. Several researchers have proven the computational efficiency and biological plausibility of higher abstracted computing systems using cortical columns [5][6] [7][8] [9]. Previous novel works in the area invoke CPUs, GPUs, GPGPUs, and other software based approaches [5][6] [7].…”

Section: Introductionmentioning

confidence: 99%

“…Several researchers have proven the computational efficiency and biological plausibility of higher abstracted computing systems using cortical columns [5][6] [7][8] [9]. Previous novel works in the area invoke CPUs, GPUs, GPGPUs, and other software based approaches [5][6] [7]. Software based approaches argue that creating hardware models for cortical systems would possess a difficult learning curve, need explicit technical definitions regarding connectivity and hierarchy, and incur debugging problems [5].…”

Section: Introductionmentioning

confidence: 99%

“…Previous novel works in the area invoke CPUs, GPUs, GPGPUs, and other software based approaches [5][6] [7]. Software based approaches argue that creating hardware models for cortical systems would possess a difficult learning curve, need explicit technical definitions regarding connectivity and hierarchy, and incur debugging problems [5]. However given the fact that these models have been implemented in software, simple hardware based factors have been disregarded.…”

Section: Introductionmentioning

confidence: 99%

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Towards Hardware Realizations of Intelligent Systems: A Cortical Column Approach

Tino

Khan

Yuan

2013

2013 42nd International Conference on Parallel Processing

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Many researchers seek for alternatives to traditional computing architectures, often placing emphasis on modeling biological systems that possess intelligence and learning capabilities. Cortical columns have emerged as a high-level unsupervised learning model for extracting independent data features in a hierarchical manner. Previous cortical models simply rely on software based techniques and neglect the actual purpose of investigating these architectures: to diverge from the conventional Von Neumann approach to an actual hardware realization of an intelligent system. This work presents the hardware realization of a cortical column system, taking several factors into consideration which were previously disregarded by software models. We introduce a Neural Spike Dual-Rail communication scheme, and a temporal pooling unit capable of detecting data distortions during training and testing. This work concludes with a study on cortical columns and their hierarchical impact on hardware resources.

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A case for neuromorphic ISAs

Cited by 31 publications

References 31 publications

BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing

BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing

An analog astrocyte–neuron interaction circuit for neuromorphic applications

Towards Hardware Realizations of Intelligent Systems: A Cortical Column Approach

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