A Cause and Cure of Stacking Faults in Silicon Epitaxial Layers

Pomerantz, D.

doi:10.1063/1.1709270

Cited by 58 publications

(13 citation statements)

References 19 publications

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“…I n order to evaluate these defects, a wafer must be subjected to proper heat treatments which increase the defect size to an observable one. Microdefects due to process contamination described above appear as saucer pits (S-pits) by a preferential etching after high temperature heat treatment [4, 9,101. I n the latter case, device characteristics such as leakage current of a bipolar device [l], lifetime of MOS capacitor [5 to 71, holding time of dynamic RAM [8], and so on are studied in connection with the IG effect.…”

Section: Introductionmentioning

confidence: 99%

Transient Behaviour of Intrinsic Gettering in CZ Silicon Wafers

Tsuya

Shimura

1983

Phys. Stat. Sol. (a)

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The transient behaviour of intrinsic gettering (IG) is clarified for the first time on the silicon wafer with surface defects introduced by the prc-annealing in wet 0, a t 1140 "C. It is found that surface defects introduced by the pre-annealing in 0, at higher temperatures, which are speculated to be heavy metal clusters in this work, migrate to an inner region and are gettered by inner defects during the post-annealing at lower temperatures such as 950 "C. These results suggest that surface defects introduced by pre-oxidation process can be gettered during device heat treatment a t comparatively lower temperatures if microdefect nuclei are suitably given.Das nichtstationare Verhalten der Intrinsic-Getterung (IG) wird erstmalig geklilrt an Siliziumscheiben mit Oberflllchendefekten, die durch die Vortemperung in feuchtem 0, bei 1140 "C eingefuhrt werden. Es wird gefunden, &I3 Oberflachendefekte, die durch eineVortemperung in 0, bei hoheren Temperaturen eingefiihrt werden und von denen in dieser Arbeit angenommen wird, daB sie Schwermetallcluster sind, in cinen inneren Bereich wandern und durch innere Defekte wiihrend der Nachtemperung bei tieferen Temperaturen, wie etwa 950 "C gegettert werden. Diese Ergebnisse zcigen, d a B Oberflachendefekte, die durch einen Vor-OxydationsprozeB erzeugt werden, wahrend einer Wilrmebehandlung bei vcrglcichsweise niedrigcren Temperaturen gegettert werden konnen, wenn geeignete Mikrodefektkeime gebildet werden. 1) 1-1, Miyazaki, Miyamae-ku, Kawasaki 213, Japan. 2) Present address: Monsanto Co., 800N Lindbergh Blvd. St. Louis, Mo. 63167.

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Section: Introductionmentioning

confidence: 99%

Transient Behaviour of Intrinsic Gettering in CZ Silicon Wafers

Tsuya

Shimura

1983

Phys. Stat. Sol. (a)

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“…The roughness of the back of wafers Z was probably responsible for gettering the fault nuclei during the oxidation process. Mechanical damage gettering has been advocated in the past (16)(17)(18)(19) to getter undesirable impurities in a way phenomenologically similar to the commonly used phosphorus diffusion gettering (29). It has not been documented that mechanical damage prevents the formation of OISP through the CMOS process.…”

Section: Experimental Procedures and Resultsmentioning

confidence: 99%

“…Gettering induced by back surface damage is not new. Pomerantz (16) had suggested the same technique to get rid of process-induced defects. Strain generated due to mechanical damage could lead to the precipitation of the impurities in the damaged region or enhance their diffusivities in the bulk silicon.…”

Section: Discussionmentioning

confidence: 99%

A Study of Stacking Faults during CMOS Processing: Origin, Elimination and Contribution to Leakage

Murarka¹,

Seidel²,

Dalton³

et al. 1980

J. Electrochem. Soc.

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If the native oxide layer is sufficiently thin, the oxidation process is controlled by reaction rate at the GaAs surface (12). Note that holes at the GaAs surface produce broken bonds of GaAs which can react with oxygen atoms, resulting in oxidation of GaAs. Therefore the thickness could be related to the hole concentration at the GaAs surface.The permittivity of the native oxide layer on GaAs, which is dependent on oxidation processes, was regarded as a parameter in the present analysis. The optical refractive indexes are 1.56 for the thermal oxide of GaAs at 5460A and 1.8 ~ 1.9 (1, 10) for the native oxide. The electrostatic permittivity for both the oxides should be correspondingly different in the similar range. In the present study, an electrostatic permittivity of 5.4 (9) for the thick anodic oxide film was employed for calculating the oxide thickness. The validity of this permittivity is supported by the fact that the optical refractive index for thin native oxide is almost identical to that for thick anodic oxide (i, I0). The relationship 6 cc n-V= is well satisfied, even if the actual permittivity is slightly different from 5.4.In conclusion, it has been clarified that the chemical activity of n-GaAs surface for oxidizing agent is remarkably enhanced with lowering of the bulk electron concentration.

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“…An optical micrograph of a-Si thin film grown on glass by thermal evaporation is shown in Figure 1(a). The observed microstructures are very familiar features in MBE grown epitaxial silicon thin films and are known as shallow saucer pits (S-pits) [16]. These structures have also been interpreted as point defects or clustered crystallographic imperfections.…”

Section: Morphology and Structurementioning

confidence: 94%

Chromium‐Induced Nanocrystallization of a‐Si Thin Films into the Wurtzite Structure

Kumar

Krishna

2008

Journal of Nanomaterials

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Chromium metal-induced nanocrystallization of amorphous silicon (a-Si) thin films is reported. The nanocrystalline nature of these films is confirmed from X-ray diffraction and Raman spectroscopy. Significantly, the deconvolution of Raman spectra reveals that the thin films were crystallized in a mixed phase of cubic diamond and wurzite structure as evidenced by the lines at 512 and 496 cm−1, respectively. The crystallite sizes were between 4 to 8 nm. Optical properties of the crystallized silicon, derived from spectral transmittance curves, revealed high transmission in the region above the band gap. Optical band gap varied between 1.3 to 2.0 eV depending on the nature of crystallinity of these films and remained unaltered with increase in Cr addition from 5 to 30%. This signifies that the electronic structure of the nanocrystalline Silicon films is not affected considerably inspite of the presence of metal silicides and the process of crystallization.

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A Cause and Cure of Stacking Faults in Silicon Epitaxial Layers

Cited by 58 publications

References 19 publications

Transient Behaviour of Intrinsic Gettering in CZ Silicon Wafers

Transient Behaviour of Intrinsic Gettering in CZ Silicon Wafers

A Study of Stacking Faults during CMOS Processing: Origin, Elimination and Contribution to Leakage

Chromium‐Induced Nanocrystallization of a‐Si Thin Films into the Wurtzite Structure

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