A new process is described which permits the sealing of metals to glass and other insulators at temperatures well below the softening point of the glass. Sealing is accomplished in about 1 min by applying a dc voltage in excess of a few hundred volts between the glass and the metal in such a way that the former is at a negative potential with respect to the latter. The process has been applied to a number of glass-metal combinations. A discussion is presented of some of the mechanisms which are believed to play a role in the bonding process.

In many applications of silicon epitaxial layers grown on silicon substrates it is necessary to oxidize the substrate and then remove the oxide prior to epitaxial deposition. This oxidation step is found to produce a greatly increased density of stacking faults in the deposit. This anomalous increase in stacking faults can be eliminated if the back (undeposited) substrate surface is treated either to abrasive processes such as lapping and scribing or to a boron-gettering process prior to oxidation. Both types of treatment are likewise found to eliminate saucer-like pits observed in oxidized slices after structural etching. The incidence of these pits is closely correlated with the incidence of stacking faults in the grown layer. It is concluded that the pits represent precipitates of fast-diffusing impurities and are probable nucleation sites for stacking faults.

Distributions of defects observed in single crystals of silicon grown from the melt are shown to be congruent with two well known growth inhomogeneities characterized either by a spiral ramp pattern or a faceted core pattern in the crystal. The consequences of these defects are traced through the oxidation of the substrate, as required for a subepitaxial diffusion, and (after removal of the oxide) the growth of an epitaxial layer. It will be shown that the defect distributions persist through these processes and, interacting with process induced defects, produce several characteristic distributions of stacking faults in the epitaxial layer.

Two types of probe measurement are described which allow the determination of the conductivity mobility and the density of majority carriers in the neighborhood of p‐n junctions. The first of these measures the change in sheet conductivity of a layer as a function of the reverse bias applied to a junction bounding the layer. The second measures the capacitance of the junction vs. the reverse bias. The techniques are applied to silicon p‐n junctions of both the epitaxial and diffused variety. A significant difference is observed in the mobility variation near these two types of junction.

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