Effects of Grown-ln and Process-Induced Defects in Single Crystal Silicon

In the present paper a preoxidation gettering procedure (called POGO) is described which prevents the formation and/or activation of stacking fault nucleation sites during oxidation. In this way the stacking faults and their possible device degrading influences are eliminated at the start of a processing schedule. In addition, the gettering medium is retained through all subsequent high temperature processing, thereby continuing to suppress the formation of stacking faults. The gettering of the nucleation sites, whether they be process induced, such as impurity precipitation, or native to the original crystal growth, such as vacancies or impurities, is achieved by the controlled introduction of interfacial misfit dislocations on the back side of the wafer. The dislocations interact with the stacking fault nucleation sites such that the nuclei diffuse from the active device side of the wafer to the line defects which are confined to within a few microns of the back surface.

“…We have, however, schematically outlined the problem as shown in Fig. 5, which is based, in part, on recent work of Pomerantz (17) and de Kock (8,18,19).…”

Section: Discussionmentioning

confidence: 99%

“…It is well established (8,17) that metallic imPurities introduced during stage II processing can become associated with stage I defects to form stacking faults during oxidation or epitaxial growth. This type of process-induced defect is most certainly gettered by the POGO misfit dislocation and/or phosphorus diffusion treatment itself.…”

Section: Discussionmentioning

confidence: 99%

Elimination of Oxidation‐Induced Stacking Faults by Preoxidation Gettering of Silicon Wafers: I . Phosphorus Diffusion‐Induced Misfit Dislocations

Rozgonyi¹,

Petroff²,

Read³

1975

“…[134][135][136][137][138][139] The defects distribute in a swirl pattern, reflecting the combined effects of melt convection, rotation of the crystal and temperature fluctuations at the crystal-melt interface during crystal growth. The observed defects reflect conditions subsequent to the complete crystal growth process, resulting from the complicated set of microscopic defect reactions in silicon.…”

Section: Dislocation-free Crystal Growthmentioning

confidence: 99%

An Electronics Division Retrospective (1952-2002) and Future Opportunities in the Twenty-First Century

Huff¹

2002

The emergence of crystalline silicon and silicon-based materials such as silicon-germanium as the premier materials and the personnel driving the integrated circuit ͑IC͒ microelectronics revolution will be reviewed. The major threshold events from the 1940s through the mid-1960s, presaging the onset of the large scale integration microelectronics era, will be highlighted. The major silicon material challenges such as dislocation-free single-crystal growth, plastic deformation, the point-defect dilemma, gettering, oxygen in silicon, carrier lifetime, and controlled point-defects in the silicon crystal during the evolution of silicon microelectronics from large scale integration through the very large scale integration era in the 1970s and the 1980s into the ultralarge scale integration era of the 1990s will then be reviewed. Opportunities in epitaxy, wafer cleaning, silicon-on-insulator, silicon-germanium, IC scaling and potential changes in device configuration and IC architecture in the evolution towards the 64 Gbit DRAM and 9 G transistor high-performance MPU logic era in 2016 ͑per the 2001 edition of the International Technology Roadmap for Semiconductors͒ will be discussed in the context of silicon-based microelectronics. The complementary role of compound semiconductors, nanoelectronics and the continuing initiative to obtain an optoelectronic system compatible with silicon will also be discussed. Finally, nonsilicon materials and device configurations will briefly be noted. © 2002 The Electrochemical Society. ͓DOI: 10.1149/1.1471893͔ All rights reserved.Available electronicallyApril 11, 2002. The computer and communications age has catapulted electronics to its current status as the dominant global industry. Indeed, we are in the midst of a revolution brought about by the availability of inexpensive information acquisition, manipulation, and distribution systems. Exploitation of electron and hole conduction in silicon has resulted in electronic memory and logic circuits such as the dynamic random access memory ͑DRAM͒ and microprocessor. Control of the interaction of photons with compound semiconductors has resulted in optical devices such as the laser and optical fiber networks. This revolution has been and will continue to be dependent on our ability to control electronic and photonic material processing techniques for the manufacture of useful devices, circuits and systems. The preparation and detailed processing sequence of a material from crystal growth through device and circuit fabrication determines the microstructure and, therefore, the electronic properties of the material and resulting device and circuit performance, yield, and reliability. Electronic materials include semiconductors, dielectrics, magnetics, piezoelectrics, optoelectronic materials, and optical fibers which may be utilized in crystalline, polycrystalline, or amorphous form. Materials are indeed the sine qua non of electronic and optical devices and circuits.An extensive list of relevant citations through 1997 is noted in Ref. ...

“…(18)(19)(20)(21). Although a number of workers have shown that stacking faults are produced in the atmospheric silicon epitaxial layer during thermal oxidation (22)(23)(24)(25)(26), none has reported the oxidation-induced Key words: gettering, tensile stress, bow of wafer, oxidationinduced stacking fault.…”

mentioning

confidence: 99%

Microdefect Elimination in Reduced Pressure Epitaxy on Silicon Wafer by Back Damage ‐ Si3 N 4 Film Technique

Tanno

Shimura

Kawamura

1981

A gettering technique which prevents microdefect formation during oxidation processes after the growth of reduced pressure Si epitaxial layer for bipolar devices is described. A gettering process which consists of protection of the back damage layer with Si3N4 film is proposed. A microdefect density in epi‐layers of ∼102 cm−2 is obtained by back damage with the Si3N4 film coating technique, on the contrary, the microdefect density reaches ∼106 cm−2without the Si3N4 film. The critical thickness of Si3N4 film to elminate microdefects in epi‐layers is obtained 2500 and 200Å for substrates without and with back damage, respectively. It is found that the gettering action is closely correlated with induced defects in the back surface (OSF, dislocation, damage line, etc.) by sandblast‐damaging and/or Si3N4 film.