A Cellular Structure for Online Routing of Digital Spiking Neuron Axons and Dendrites on FPGAs

Shayani, Hooman; Bentley, Peter J.; Tyrrell, Andy M.

doi:10.1007/978-3-540-85857-7_24

Cited by 12 publications

(6 citation statements)

References 21 publications

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“…Table 4 summarizes related FPGA-based brain-modeling works. Designs using the Quadratic IaF model such as the work in [18,17] can implement spike latencies, activitydependent thresholds and bistability properties of resting and tonic 3 spiking. This model requires only 7 FP operations per 1ms for each neuron making it useful for the exploration of large neuron integrator networks.…”

Section: Comparison To Related Workmentioning

confidence: 99%

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FPGA-based biophysically-meaningful modeling of olivocerebellar neurons

Smaragdos

Isaza

Eijk

et al. 2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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The Inferior-Olivary nucleus (ION) is a well-charted region of the brain, heavily associated with sensorimotor control of the body. It comprises ION cells with unique properties which facilitate sensory processing and motor-learning skills. Various simulation models of ION-cell networks have been written in an attempt to unravel their mysteries. However, simulations become rapidly intractable when biophysically plausible models and meaningful network sizes (≥100 cells) are modeled. To overcome this problem, in this work we port a highly detailed ION cell network model, originally coded in Matlab, onto an FPGA chip. It was first converted to ANSI C code and extensively profiled. It was, then, translated to HLS C code for the Xilinx Vivado toolflow and various algorithmic and arithmetic optimizations were applied. The design was implemented in a Virtex 7 (XC7VX485T) device and can simulate a 96-cell network at real-time speed, yielding a speedup of ×700 compared to the original Matlab code and ×12.5 compared to the reference C implementation running on a Intel Xeon 2.66GHz machine with 20GB RAM. For a 1,056-cell network (non-real-time), an FPGA speedup of ×45 against the C code can be achieved, demonstrating the design's usefulness in accelerating neuroscience research. Limited by the available on-chip memory, the FPGA can maximally support a 14,400-cell network (non-real-time) with online parameter configurability for cell state and network size. The maximum throughput of the FPGA IONnetwork accelerator can reach 2.13 GFLOPS.

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Section: Comparison To Related Workmentioning

confidence: 99%

“…Shayani et al [18,17] proposed a neuron model using a Quadratic IaF model [10,9] which enabled simulating extra dendritic and axonal properties. The system supported on-line network-topology adaptation.…”

Section: Related Workmentioning

confidence: 99%

FPGA-based biophysically-meaningful modeling of olivocerebellar neurons

Smaragdos

Isaza

Eijk

et al. 2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…Although this strategy is appropriate for skipping just the damaged resources, and consequently maximize the amount of non-damaged useful area, the routing possibilities are limited by the slots defined at design time. This limitation can be overcome by using the MDR method [41]. In this work, the routing primitive hard-macros are freely placed as long as their size is a multiple of the allocated modules size.…”

Section: Online Routingmentioning

confidence: 99%

A Roadmap for Autonomous Fault-Tolerant Systems

Iturbe

Benkrid

Arslan

et al. 2010

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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An Autonomous Fault-Tolerant System (AFTS) refers to a system that is able to configure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain its functionality. This work analyzes how AFTS could be built, specifically focusing on hardware platform dependant issues, and gives an overview of the state-of-the-art in this field, which is still in its infancy. Three technological levels are used for classifying the research efforts conducted to date. By describing the current state-of-the-art and the constraints imposed by current technology, this work tries to envision future trends towards the ultimate objective of achieving a fully-adaptive system capable of modifying its architecture on-the-fly as needed. Finally, the general structure and organization of a Reliable Reconfigurable Real-Time Operating System (R3TOS) is presented. This OS aims at making the aforementioned adaptability easily exploitable by future commercial applications.

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“…Traditionally, software approaches are too slow to execute a long simulation of SNNs and do not scale efficiently [4]. Thus, researchers have explored alternative hardware SNN solutions using FPGAs and GPUs that provide a fine-grained parallel architecture and a 2D mesh interconnect topology [5], [6]. The authors highlight [4] that FPGA approaches have several limitations such as inefficient area utilisation and a Manhattan style interconnect.…”

Section: Motivation and Previous Workmentioning

confidence: 99%

An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations

Carrillo

Harkin

McDaid

et al. 2010

Evolvable Systems: From Biology to Hardware

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Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However the use of the NoC as an interconnection fabric for large scale SNN (i.e. beyond a million neurons) demands a good trade-off between scalability, throughput, neuron/synapse ratio and power consumption. In this paper an adaptive NoC router architecture is proposed as a way to minimise network delay across varied traffic loads. The novelty of the proposed adaptive NoC router is twofold; firstly, its adaptive scheduler combines the fairness policy of a round-robin arbiter and a first-come first-served priority scheme to improve SNN spike packet throughput; secondly, its adaptive routing scheme (verified using simulated SNN traffic) allows the selection of different NoC router output ports to avoid traffic congestion. The paper presents the performance and synthesis results of the proposed adaptive NoC router operating within the EMBRACE architecture. Results illustrate that the high-throughput, low area and low power consumption of the adaptive NoC router make it feasible for use in large scale SNN hardware implementations.

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A Cellular Structure for Online Routing of Digital Spiking Neuron Axons and Dendrites on FPGAs

Cited by 12 publications

References 21 publications

FPGA-based biophysically-meaningful modeling of olivocerebellar neurons

FPGA-based biophysically-meaningful modeling of olivocerebellar neurons

A Roadmap for Autonomous Fault-Tolerant Systems

An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations

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