A checkpoint/restore framework for systemc-based virtual platforms

Kraemer, Stefan; Leupers, Rainer; Petras, Dietmar; Philipp, Thomas

doi:10.1109/socc.2009.5335656

Cited by 11 publications

(7 citation statements)

References 8 publications

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“…While rollback has never been considered for optimistic PDES of SystemC models due to its cost and complexity, it has been used for other purposes. For instance, [31] proposes a Checkpoint/Restore (C/R) framework for SystemC virtual platform that enables resuming a regular SystemC simulation at different points for debugging purpose. In a completely different approach, [32] proposes to rely on posix's fork() to recover from timing errors caused by temporal decoupling.…”

Section: Conflict Recovery With Rollbackmentioning

confidence: 99%

Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support

et al. 2021

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Section: Conflict Recovery With Rollbackmentioning

confidence: 99%

Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support

et al. 2021

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“…Since it operates on the entire process, it works even with closed-source SystemC modules. Compared to other methods that use snapshots of the entire process, such as [11], our method can operate fully in-memory, without having to save images to disk. This makes rolling back to checkpoints created within one same simulation much faster than [11], where several seconds are necessary to store and load the snapshots.…”

Section: Dynamic Checkpointing When Inside the Vpsimmentioning

confidence: 99%

Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration

Charif

Busnot

Mameesh

et al. 2019

Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools

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Virtual Prototyping has been widely adopted as a costeffective solution for early hardware and software co-validation. However, as systems grow in complexity and scale, both the time required to get to a correct virtual prototype, and the time required to run real software on it can quickly become unmanageable. This paper introduces a feature-rich integrated virtual prototyping solution, designed to meet industrial needs not only in terms of performance, but also in terms of ease, rapidity and automation of modelling and exploration. It introduces novel methods to leverage the QEMU dynamic binary translator and the abstraction levels offered by SystemC/TLM 2.0 to provide the best possible trade-offs between accuracy and performance at all steps of the design. The solution also ships with a dynamic platform composition infrastructure that makes it possible to model and explore a myriad of architectures using a compact high-level description. Results obtained simulating a RISC-V SMP architecture running the PARSEC benchmark suite reveal that simulation speed can range from 30 MIPS in accurate simulation mode to 220 MIPS in fast functional validation mode.

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“…In [29] a strategy is presented to release external resources when starting the checkpointing phase and reconnect them again when restoring the simulation.…”

Section: Related Workmentioning

confidence: 99%

“…Other checkpoint implementation based on process checkpointing [29] presents results for a simple SoC 15 system using more than 400 MB for checkpoint data, growing linearly with the complexity of the design.…”

Section: Checkpoint Sizementioning

confidence: 99%