Checkpointing for Virtual Platforms and SystemC-TLM

Montón, Màrius; Engblom, Jakob; Burton, Mark

doi:10.1109/tvlsi.2011.2181881

Cited by 9 publications

(10 citation statements)

References 8 publications

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“…There is no a native way to integrate SystemC models into QEMU, thus some co-simulation approaches have been proposed in the past [10,12,13,16]. The intent of [10] is to facilitate the development of software and device drivers for whatever operating system without spending too much effort on modifying the virtual platform itself by plugging SystemC TLM 2.0 models into the QEMUbased virtual platform.…”

Section: Qemumentioning

confidence: 99%

“…The intent of [10] is to facilitate the development of software and device drivers for whatever operating system without spending too much effort on modifying the virtual platform itself by plugging SystemC TLM 2.0 models into the QEMUbased virtual platform. This work is further extended in [13] where the authors introduce a checkpoint-based feature to save and restore the SystemC state into the simulator. Alternatively, in [12,16], the authors propose a QEMU/SystemCbased framework for virtual platform prototyping that cannot only estimate the performance of a target system, but also co-simulate with hardware models down to the cycle accurate level.…”

Section: Qemumentioning

confidence: 99%

“…2 is proposed. Similarly to the approaches presented in [10,13], it reflects the traditional operating system-based stack where software applications interact with hardware peripherals through device drivers. The target platform, where software applications run, is emulated by using, indifferently, QEMU or OVP, and it is connected to a SystemC hardware peripheral through a virtual PCI 3 device, a SystemC bridge and a device driver for the target operating system.…”

Section: Co-simulation Architecturementioning

confidence: 99%

“…Furthermore, effective virtual prototyping approaches cannot exclude design reuse and bottom-up component-based design, where already defined (SystemC) models are integrated in new prototypes, to reduce the time to market. For this reason, several approaches, like [10][11][12][13], propose the use of QEMU, for efficient instruction set simulation, in combination with SystemC, for specification and reuse of customized HW components. In particular, [10] proposes a QEMU-SystemC approach developed by the GreenSoCs company which represents the main way for connecting SystemC models, as peripherals, to QEMU.…”

Section: Introductionmentioning

confidence: 99%

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On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms

Lonardi

Pravadelli

2015

VLSI-SoC: Internet of Things Foundations

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International audienceVirtual prototyping allows designers to set up an electronic system level software simulator of a full HW/SW platform to carry out SW development and HW design almost in parallel. To achieve the goal virtual prototyping tools allow the co-simulation between an efficient instruction set simulator, mainly based on dynamic binary translation of the target code, and simulation kernels for HW models, described by means of traditional hardware description languages, like, for example, SystemC. In this context, some approaches have been proposed for co-simulation between QEMU and SystemC, both from EDA companies and academic research groups. On the contrary, no paper addresses integration between Open Virtual Platform (OVP) and SystemC. Indeed, OVP models and the related simulator can be integrated into SystemC designs by using TLM 2.0 wrappers and opportune OVP APIs. However, this solution presents some disadvantages, like the incapability of supporting cycle-accurate models, and the necessity of re-design, in terms of SystemC modules, all OVP components that should be integrated in the target platform. To avoid such drawbacks, and provide an easy way to port SystemC models from a QEMU-based to an OVP-based virtual platform and vice versa, this paper presents a common co-simulation approach that works for integrating SystemC components with both QEMU and OVP. Experimental results show the effectiveness of the proposed architecture

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Section: Qemumentioning

confidence: 99%

Section: Qemumentioning

confidence: 99%

Section: Co-simulation Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms

Lonardi

Pravadelli

2015

VLSI-SoC: Internet of Things Foundations

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“…Several researchers have developed simulation platforms using QEMU and SystemC such as [9][10] [11]. Some of them support simulation of multicore architectures, but to the best of our knowledge, they are not used for simulation of NoCs with more than 100 cores.…”

Section: Related Workmentioning

confidence: 99%

A Fast Network-on-Chip Simulator with QEMU and SystemC

Nakajima

Hieda

Taniguchi

et al. 2012

2012 Third International Conference on Networking and Computing

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Network-on-Chip (NoC) is considered as a promising interconnection scheme for many-core System-on-a-Chip (SoC) since it offers better scalability than traditional bus-based interconnection. In this work, we have developed a fast simulator of NoC architectures using QEMU and SystemC. QEMU is an open-source CPU emulator which is widely used in many simulation platforms such as Android Emulator. In the proposed simulator, each CPU core is emulated by a QEMU, and the network part including NoC routers is modeled with SystemC. The SystemC simulator and QEMUs are connected by TCP sockets on a host computer. Our simulator is fast because QEMUs run in parallel on a multi-core host computer or even multiple host computers. Also, our simulator is highly retargetable because QEMU provides a variety of CPU models and we use QEMU as is. In our experiments, our simulator successfully simulates a 108-core NoC in a practical time. We have also confirmed the scalability and retargetability of our NoC simulator.

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