A circuit level fault model for resistive opens and bridges

Li, Zhuo; Lü, Xiang; Qiu, Wangqi; Shi, Weiping; Walker, D.M.H.

doi:10.1109/vtest.2003.1197678

Cited by 31 publications

(5 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fault models for digital circuits have been developed for different types of failure mechanisms like signal line bridges [4], transistor stuck-opens [5] or failures due to increasing circuit delays [6]. Another trend has emerged to develop general fault modeling mechanisms and corresponding test tools that can effectively analyze arbitrary fault types.…”

Section: Introductionmentioning

confidence: 99%

Mixed-level identification of fault redundancy in microprocessors

Oyeniran

Ubar

Jenihhin

et al. 2019

2019 IEEE Latin American Test Symposium (LATS)

View full text Add to dashboard Cite

A new high-level implementation independent functional fault model for control faults in microprocessors is introduced. The fault model is based on the instruction set, and is specified as a set of data constraints to be satisfied by test data generation. We show that the high-level test, which satisfies these data constraints, will be sufficient to guarantee the detection of all non-redundant low level faults. The paper proposes a simple and fast simulation based method of generating test data, which satisfy the constraints prescribed by the proposed fault model, and a method of evaluating the highlevel control fault coverage for the proposed fault model and for the given test. A method is presented for identification of the high-level redundant faults, and it is shown that a test, which provides 100% coverage of non-redundant high-level faults, will also guarantee 100% non-redundant SAF coverage, whereas all gate-level SAF not covered by the test are identified as redundant. Experimental results of test generation for the execution part of a microprocessor support the results presented in the paper.

show abstract

Section: Introductionmentioning

confidence: 99%

Mixed-level identification of fault redundancy in microprocessors

Oyeniran

Ubar

Jenihhin

et al. 2019

2019 IEEE Latin American Test Symposium (LATS)

View full text Add to dashboard Cite

show abstract

“…The classical fault diagnosis algorithms follow two different paradigms: cause-effect and effect-cause analysis [ 6 ]. The cause-effect approach begins with mapping the causes of failure to a specific fault type e.g.…”

Section: Introductionmentioning

confidence: 99%

“…Traditional approaches to the cause-effect fault diagnosis lay on the stuck-at fault model. Many researchers have focused on developing new fault models for particular types of failure mechanisms like signal line bridges [ 6,8 ], transistor stuck-opens [ 9,10 ] or failures due to changes in circuit delays [ 11 ]. Another trend has been to develop general fault modelling mechanisms and corresponding test tools that can effectively analyse arbitrary fault types like in [ 12 ] where D-cubes are used to model any arbitrary change in the logic function of a circuit block.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical physical defect reasoning in digital circuits

Kostin¹,

Ubar²,

Raik³

et al. 2011

Estonian J. Eng.

View full text Add to dashboard Cite

We propose a hierarchical physical defect-oriented approach for fault diagnosis in combinational digital circuits. We present the circuit as a network of modules. As modules we consider either library components (e.g. complex gates) of digital circuits or arbitrary subcircuits. The higher level fault diagnosis is carried out in two phases. In the first phase, faulty modules are located by cause-effect analysis using high-level faulty module dictionary. The size of the dictionary depends linearly on the number of modules in the circuit. In the second phase, the set of suspected faulty modules is pruned by reasoning of the defective behaviour. At the lower level, the physical defects are directly located in suspected faulty modules using defect libraries of the modules or by effect-cause reasoning inside the module. The proposed approach to fault diagnosis helps to cope with the growing complexities of digital circuits. The experimental results show high module-level diagnostic resolution of the proposed approach.

show abstract

“…In other words, a particular range of resistive fault values is detectable at the one voltage, but not at a lower voltage. The study in [4] looked at resistive bridging faults that cause stuck faults.There have been more recent studies showing how bridging faults can cause timing failures [12,13]. It is reported in [12] that the delay caused by bridge resistance can either increase or decrease depending on the input patterns.…”

Section: Very Low Voltage Testingmentioning

confidence: 99%

“…The study in [4] looked at resistive bridging faults that cause stuck faults.There have been more recent studies showing how bridging faults can cause timing failures [12,13]. It is reported in [12] that the delay caused by bridge resistance can either increase or decrease depending on the input patterns. This claim is further supported by [16] where a basic fault coverage analysis has been done on for a CMOS bridging fault at different power supplies.…”

Section: Very Low Voltage Testingmentioning

confidence: 99%