Dynamic Voltage Scaling Aware Delay Fault Testing

Ali, Noohul Basheer Zain; Zwoliński, Mark; Al-Hashimi, Bashir M.; Harrod, P.

doi:10.1109/ets.2006.13

Cited by 23 publications

(1 citation statement)

References 14 publications

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“…It has been shown that reducing the supply voltage increases the transistor channel resistance, which results in an increasing electrical impact of a gate-drain (or gatesource) resistive bridge defect, or a drain (or source) resistive open defect [10]. Circuit test under varying operating conditions has been studied in many works such as [24,25], which investigate the effect of supply voltage on the circuit delay and delay testing. The very-Low-Voltage test is exploited to detect ELF-related defects in [7,8].…”

Section: State Of the Artmentioning

confidence: 99%

Identifying Resistive Open Defects in Embedded Cells under Variations

Najafi-Haghi

Wunderlich

2023

J Electron Test

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Small Delay Faults (SDFs) due to weak defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is within the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its observability is restricted. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defective devices without a major impact on yield.

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