A circuit-level implementation of fast, energy-efficient CMOS comparators for high-performance microprocessors

Ergin, Oğuz; Ghose, Kanad; Küçük, Gürhan; Ponomarev, Dmitry

doi:10.1109/iccd.2002.1106757

Cited by 17 publications

(19 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The issue queue thus demands the use of non-traditional fast comparators that dissipate energy only (or predominantly) on a full match and little or no energy on a partial match [1,2,5]. Such designs are significantly more energy-efficient than the traditional designs.…”

Section: Non-traditional Comparatorsmentioning

confidence: 99%

“…One of the artifacts of a superscalar processor, where the mismatches in the comparands are much more frequent than the full matches is the issue queue [1,5]. The issue queue thus demands the use of non-traditional fast comparators that dissipate energy only (or predominantly) on a full match and little or no energy on a partial match [1,2,5].…”

Section: Non-traditional Comparatorsmentioning

confidence: 99%

“…In the case of the issue queue, only a few bits -no more than 8 -need to be compared. A non-traditional comparator design, as introduced in [1], which is superior to the traditional design, both in terms of energy and delay, is shown in Figure 2. This circuit compares two 8-bit comparands, A7A6...A0 and B7B6...B0.…”

Section: Non-traditional Comparatorsmentioning

confidence: 99%

“…Consequently, significant energy savings can be realized if comparators and associative logic can be designed to dissipate energy only on a full match and little or no energy on a mismatch. In recognition of this inefficiency, first noticed in [2], a series of such dissipate-on-match comparator (DMC) designs have been recently introduced [1], [5].…”

Section: Introductionmentioning

confidence: 99%

“…Section 3 describes several design alternatives for the long comparators. These designs are based on the use of several traditional comparators, several non-traditional comparator designs (as introduced in [1] or [5]) or a combination of the traditional and non-traditional designs. The choice of a specific design for a long comparator is actually dependent on the distribution of the bit patterns that are compared, which are usually obtained through microarchitectural-level simulations.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Power efficient comparators for long arguments in superscalar processors

Ponomarev

Küçük

Ergin

et al. 2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

View full text Add to dashboard Cite

Traditional pulldown comparators that are used to implement associative addressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the comparands. As mismatches occur much more frequently than matches in many situations, such circuits are extremely energy-inefficient. In recognition of this inefficiency, a series of dissipate-on-match comparator designs have been proposed to address the power considerations. These designs, however, are limited to at most 8-bit long arguments.In this paper, we examine the designs of energy-efficient comparators capable of comparing arguments as long as 32 bits in size. Such long comparands are routinely used in the load-store queues, caches, BTBs and TLBs. We use the actual layout data and the realistic bit patterns of the comparands (obtained from the simulated execution of SPEC 2000 benchmarks) to show the energy impact from the use of the new comparators. In general, a non-trivial combination of traditional and dissipate-on-match 8-bit comparator blocks represents the most energy-efficient and fastest solution. As an example of this general approach, we show how fast and energy-efficient comparators can be designed for comparing addresses within the load-store queue of a superscalar processor.

show abstract

Section: Non-traditional Comparatorsmentioning

confidence: 99%

Section: Non-traditional Comparatorsmentioning

confidence: 99%

Section: Non-traditional Comparatorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Power efficient comparators for long arguments in superscalar processors

Ponomarev

Küçük

Ergin

et al. 2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

View full text Add to dashboard Cite

show abstract

Power-aware out-of-order issue logic in high-performance microprocessors

Weinraub

Weiss

2006

Microprocessors and Microsystems

View full text Add to dashboard Cite

Reducing power dissipation of register alias tables in high-performance processors

Küçük¹,

Ergin²,

Ponomarev³

et al. 2005

IEE Proc., Comput. Digit. Tech.

Self Cite

View full text Add to dashboard Cite

Modern microprocessor designs implement register renaming using register alias tables (RATs) which maintain the mapping between architectural and physical registers. Because of the non-trivial power that is dissipated in a disproportionately small area, the power density in the RAT is significantly higher than in some other datapath components. Mechanisms are proposed to reduce the RAT power and the power density by exploiting the fundamental observation that most of the generated register values are used by the instructions in close proximity to the instruction producing a value. The first technique disables the RAT lookup for a source register if that register is a destination of an earlier instruction dispatched in the same cycle. The second technique eliminates some of the remaining RAT read accesses, even if the source register value is produced by an instruction dispatched in an earlier cycle. This is done by buffering a small number of recent register address translations in a set of external latches and satisfying some RAT lookup requests from these latches. The net result of applying both techniques is a 30% reduction in the RAT energy with no performance penalty, little additional complexity and no cycle time degradation.

show abstract

A circuit-level implementation of fast, energy-efficient CMOS comparators for high-performance microprocessors

Cited by 17 publications

References 9 publications

Power efficient comparators for long arguments in superscalar processors

Power efficient comparators for long arguments in superscalar processors

Power-aware out-of-order issue logic in high-performance microprocessors

Reducing power dissipation of register alias tables in high-performance processors

Contact Info

Product

Resources

About