A circuit-level substrate current model for smart-power ICs

Conte, Fabrizio Lo; Sallèse, Jean-Michel; Pastre, Marc; Krummenacher, F.; Kayal, Maher

doi:10.1109/ecce.2009.5316405

Cited by 4 publications

(2 citation statements)

References 14 publications

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“…Addressing more complex structure with this methodology could be impractical as it takes excessively long time. In [3], the PN junction and resistor models were modified by additional terminal to take into account the minority carrier concentrations and gradients at the boundaries. These enhanced models can be used to create a substrate network which considers the minority carriers propagation in the substrate.…”

mentioning

confidence: 99%

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Moursy

Zeng

Khalil

et al. 2017

IEEE Trans. Power Electron.

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Abstract-This paper presents a methodology to analyze the substrate noise coupling and reduce their effects in smart power integrated circuits. This methodology considers the propagation of minority carriers in the substrate. Hence, it models the lateral bipolar junction transistors that are layout dependent and are not modeled in conventional substrate extraction tools. It allows the designer to simulate substrate currents and check their effects on circuits functionality. The proposed methodology employs a dedicated tool for substrate network generation referred to as AUTOMICS. We applied the methodology on two test cases. The first case is a DC-DC buck converter chip fabricated with a 0.35 µm HV-CMOS technology. The DC coupling current between the switches and the bandgap circuit is simulated and verified with measurements. The second test case is an automotive industrial chip that has a latch-up failure due to substrate coupling. In transient simulations, the failure has been reproduced as in measurements. This highlights the stronghold of the methodology since it can be used to prevent this type of failures before fabrication. The proposed methodology can reduce the number of redesigns in the automotive industry. Hence, it shortens the time-to-market, improves the robustness of the design, and reduces the cost.

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mentioning

confidence: 99%

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Moursy

Zeng

Khalil

et al. 2017

IEEE Trans. Power Electron.

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show abstract

“…In [4], a modeling methodology for the PN junctions contributing in the substrate noise has been introduced. Additional terminals to the conventional diodes and resistors are used to preserve the minority carrier diffusion.…”

Section: Introductionmentioning

confidence: 99%

Towards Automatic Diagnosis of Minority Carriers Propagation Problems in HV/HT Automotive Smart Power ICs

Moursy

Zeng

Iskander

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-In this paper, a proposed methodology to identify the substrate coupling effects in smart power integrated circuits is presented. This methodology is based on a tool called AUTOMICS to extract substrate parasitic network. This network comprises diodes and resistors that are able to maintain the continuity of minority carrier concentration. The contribution of minority carriers in the substrate noise is significant in high-voltage and high temperature applications. The proposed methodology along with conventional latch-up problem identification for a test case automotive chip AUTOCHIP1 are presented. The time of the proposed methodology is significantly shorter than the conventional one. The proposed methodology could significantly shorten the time-to-market and ameliorate the robustness of the design.

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Progress on single-electron transistors

Jehl

Sanquer

2010

2010 IEEE International Conference on Integrated Circuit Design and Technology

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A circuit-level substrate current model for smart-power ICs

Cited by 4 publications

References 14 publications

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Towards Automatic Diagnosis of Minority Carriers Propagation Problems in HV/HT Automotive Smart Power ICs

Progress on single-electron transistors

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