A clock-gating based capture power droop reduction methodology for at-speed scan testing

Yang, Bo; Sanghani, Amit; Sarangi, Shantanu; Liu, Chunsheng

doi:10.1109/date.2011.5763042

Cited by 11 publications

(8 citation statements)

References 12 publications

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“…Since timing of the V droop hotspots is critical in multi-clock domain patterns, care is taken to further reduce the global noise problem by staggering the high frequency clock domains during capture. More details on the architecture can be found in [1].…”

Section: B Principle Of Lp-dft Architecturementioning

confidence: 99%

“…To address this and reduce Test Mode Capture PSN, the low power (LP) DFT controller [1] was added which can be programmed to constrain simultaneous switching at different activity levels (LP 6.25%, LP 12.5%,…,LP 93.75%) but the power budget needs to be pre-determined before pattern generation. Since ATPG tools have no knowledge of chip layout, they estimate overall flop-to-flop toggle.…”

Section: A Motivation On Gpusmentioning

confidence: 99%

“…At the sub-block level, the JTAG-programmable LP-DFT Controller scheme in [1] groups all the clock gates in the design into n groups. Each group is controlled by a unique output of the controller.…”

Section: B Principle Of Lp-dft Architecturementioning

confidence: 99%

See 2 more Smart Citations

Test method and scheme for low-power validation in modern SOC integrated circuits

Bhaskaran

Sanghani

Narayanun

et al. 2016

2016 IEEE 34th VLSI Test Symposium (VTS)

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Test Mode power can be 5X higher than functional power in GPUs, while the power grid is designed only for worstcase functional toggle. The large simultaneous switching noise induced on the power rails during at-speed capture testing is constrained by means of hardware solution. To determine the best low power mode for ATPG, we propose novel techniques to: estimate global peak current (di), determine local droop trend and validate and further optimize chosen power settings with exhaustive post-silicon power mode tuning. During Power Optimization (PO) phase, the measured clock frequency (fclk) and Vdroop are analyzed on every pattern and test coverage and pattern count are optimized for the production pattern set. We share correlation results and Power Supply Noise (PSN) distribution for the production pattern set on recent 28-nm GPUs.

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Section: B Principle Of Lp-dft Architecturementioning

confidence: 99%

Section: A Motivation On Gpusmentioning

confidence: 99%

See 1 more Smart Citation

Test method and scheme for low-power validation in modern SOC integrated circuits

Bhaskaran

Sanghani

Narayanun

et al. 2016

2016 IEEE 34th VLSI Test Symposium (VTS)

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show abstract

“…Test power dissipation is known to be 2× the functional power dissipation in CPUs [22] and 4× the functional power dissipation in GPUs [35]. If the power dissipated during tests go beyond the rated power of the device then it is possible for a good device to fail or even be damaged.…”

Section: Introductionmentioning

confidence: 99%

ATE test time reduction using asynchronous clock period

Venkataramani

Agrawal

2013

2013 IEEE International Test Conference (ITC)

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“…The capture path for the flip-flops in the macro comes from outside and this is the area of concern for us. Extended work targeting clock gating during capture was proposed in [3,4]. In this paper, we propose a method to facilitate hard macro debug using existing test control logic.…”

mentioning

confidence: 99%

On Handling Memory Scan Chains

Bansal

Mendhalkar

Tekumalla³

2014

2014 IEEE 23rd North Atlantic Test Workshop

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Memories from the Library vendor come as a hard macro in the design. With the increased focus on meeting timing requirements, memories are provided in an integrated form from vendor. These integrated memory hard macros not only consist of SRAM read-write behavior but also comprise of scan chains and bypass logic around SRAM. This bypass logic consists of shadow cells which are already stitched into small scan chains inside the hard macro. Since this whole memory bypass and shadow logic is inside hard macro, it can be treated as a separate timing closed module in the design. Because of the separate timing closure process, there can be an occurrence of timing violation during silicon test on the logic interface between the SoC and the hard macro. There is a need to have an optional mode where designer should have freedom to generate the patterns with or without consideration of the capture mode of the memory scan cells. In this paper, we present a methodology to handle memory scan chains by controlling the memory clock during capture, using a combination of control signals which already exist in the design.

show abstract

A clock-gating based capture power droop reduction methodology for at-speed scan testing

Cited by 11 publications

References 12 publications

Test method and scheme for low-power validation in modern SOC integrated circuits

Test method and scheme for low-power validation in modern SOC integrated circuits

ATE test time reduction using asynchronous clock period

On Handling Memory Scan Chains

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