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We present the design and implementation details of a time-division demultiplexing/multiplexing based scan architecture using serializer/deserializer. This is one of the key DFT features implemented on NVIDIA's Fermi family GPU (Graphic Processing Unit) chips. We provide a comprehensive description on the architecture and specifications. We also depict a compact serializer/deserializer module design, test timing consideration, design rule and test pattern verification. Finally, we show silicon data collected from Fermi GPUs.

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Graphics Processing Unit (GPU) requires I/O bandwidth of the order of Gbps which can be met by implementation of High Speed Serializer/Deserializer differential I/Os with clock embedded in data stream, traditionally tested using functional Built In Self Test (BIST). Implementation of these I/Os on complex graphics chip poses requirement for fault grading these I/Os. This paper presents the challenges involved in fault grading SerDes I/Os used in Nvidia's GPU chips and proposes methodology for extracting fault coverage numbers using industry standard tools.

Test Mode power can be 5X higher than functional power in GPUs, while the power grid is designed only for worstcase functional toggle. The large simultaneous switching noise induced on the power rails during at-speed capture testing is constrained by means of hardware solution. To determine the best low power mode for ATPG, we propose novel techniques to: estimate global peak current (di), determine local droop trend and validate and further optimize chosen power settings with exhaustive post-silicon power mode tuning. During Power Optimization (PO) phase, the measured clock frequency (fclk) and Vdroop are analyzed on every pattern and test coverage and pattern count are optimized for the production pattern set. We share correlation results and Power Supply Noise (PSN) distribution for the production pattern set on recent 28-nm GPUs.