Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips

Sanghani, Amit; Yang, Bo; Natarajan, K.; Liu, Chunsheng

doi:10.1109/vts.2011.5783724

Cited by 25 publications

(8 citation statements)

References 12 publications

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“…More recently [10] describes the practical aspects of implementing a time-division multiplexed TAM for GPUs. They also write a wrapper script to serialize the patterns and their key contribution is in their detailed descriptions of the DFT insertion, rule checking and verification.…”

Section: Previous Workmentioning

confidence: 99%

SmartScan - Hierarchical test compression for pin-limited low power designs

Chakravadhanula

Chickermane

Pearl

et al. 2013

2013 IEEE International Test Conference (ITC)

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IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that high quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead.

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Section: Previous Workmentioning

confidence: 99%

SmartScan - Hierarchical test compression for pin-limited low power designs

Chakravadhanula

Chickermane

Pearl

et al. 2013

2013 IEEE International Test Conference (ITC)

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“…The scan frequency is limited by thermal and design constraints; the scan chain insertion is not optimized for performance, and therefore the scan frequency is usually limited to a few tens of MHz. Most of the conventional TAM design methods, therefore, rely on either increasing the number of test channels, which is limited by the chip pins or increasing the pin efficiency by techniques such as TDMA and SerDes [15] [16][17] [18].…”

Section: Background and Motivationmentioning

confidence: 99%

“…Time de-multiplexers at the receiving end perform the serial to parallel conversion, and the data is shifted into scan-chains at the scan frequency. Another approach to allow optimal utilization of tester resources was presented in [17] and [18]. In [17], the authors introduced the concept of virtual TAMs to efficiently utilize tester resources.…”

Section: Prior Workmentioning

confidence: 99%

Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports

Soomro

Samie

Jennions

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In order to meet the increasing demand for more performance with reduced power consumption and chip formfactor, semiconductor manufacturing is moving towards 3D Stacked Integrated Circuits (SIC). One of the challenges in bringing this technology into realization is the complicated test accessibility requirements of 3D chips, which apart from having adequate defect coverage, should also have minimal test time. A major limiting factor in test time improvement of ICs is the number of chip terminals, such as pins or Through Silicon Vias (TSVs) available for bulk vector transport in testing. In the conventional design, a chip terminal is only used to either send or receive data at any given time. In this paper, a test accessibility architecture based on ternary encoded Simultaneous Bi-Directional Signaling (SBS), intended for use in parallel Test Access Mechanism (TAM) in System on Chip (SoC) based designs, is proposed. This method enables the use of chip terminals to simultaneously send and receive test vectors, effectively doubling the per-pin efficiency during testing. Experiments show that this technique reduces the Overall Test Time (OTT) by up to 53.6% as compared to conventional TAM design methods. Index Terms-3D Stacked Integrated Circuits, System on Chip, Design for Testability, Simultaneous Bi-directional, Test Access Mechanism© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2 the industry by the International Technology Roadmap for Semiconductors (ITRS) [11].In this paper, a novel Test Access Mechanism (TAM) design is proposed for 3D SICs that doubles the data transfer efficiency of the pins and TSVs, resulting in a substantial decrease of the test times. This is achieved by leveraging Simultaneous Bidirectional Signaling (SBS) for full-duplex test mode communication at chip terminals. SBS allows transmission and reception of test bits simultaneously compared to the conventional Uni-Directional Signaling (UDS) scheme in which the signal could travel in only one direction at a given time. Using SBS, a complete transmission and reception channel could be formulated using a single electrical path at the chip terminal instead of two, effectively doubling the number of test-channels and increased parallelism in test scheduling. The paper further discusses the TAM design considerations for the incorporation of SBS in 3D SICs such that it does not interfere with the functional mode performance and standard DFT logic, such as JTAG compliant boundary scan registers. An example implementation suitable for low-frequency test vector transportation is presented, and its electrical characteristics are discu...

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“…Time-division multiplexing is the standard method of maximizing ATE bandwidth utilization when the ATE shift speed is higher than the internal scan chain shift speed and has been successfully applied to combinational scan compression methods [10], [12]. However, for large designs with many scan chains the number of combinational compressor inputs and outputs (I/O) can exceed the number of virtual pins available after time-division; consequently, shift speed must be reduced or compressors must be shared -neither of Details of these advantages are explained in the next section.…”

Section: Chip Level Time-division Multiplexing: Serdes and Pipelinesmentioning

confidence: 99%

“…Even low-cost ATEs can drive test channels around 200MHz whereas internal scan chains operate at a much lower frequency of 10MHZ to 50MHz [10]. Test compression, particularly combinational methods that add long compressor logic paths at either end of scan chains can further widen the gap by requiring even lower internal shift speed.…”

Section: Introductionmentioning

confidence: 99%

Achieving extreme scan compression for SoC Designs

Wohl

Waicukauski

Colburn³

et al. 2014

2014 International Test Conference

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High volume testing of complex System on Chip (SoC) designs at reasonable test cost requires high test data and test time compression. We present a multilevel scan compression architecture that combines a flexible test compression core with an efficient dynamic broadcast structure and a high speed data access technique. Full X-tolerance, power-aware scan shift and diagnosis are supported through the entire architecture. We present a flow for assembling the various components that limits the impact on area and timing by minimizing test signals and improving modularity of the inserted design-for-test (DFT) structures. These techniques provided a reduction of 600x in test data volume and over 2300x in test time on large Graphics Processor Units (GPU) designs.

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Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips

Cited by 25 publications

References 12 publications

SmartScan - Hierarchical test compression for pin-limited low power designs

SmartScan - Hierarchical test compression for pin-limited low power designs

Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports

Achieving extreme scan compression for SoC Designs

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