A CMOS 3.1-10.6GHz UWB LNA Employing StaggerCompensated Series Peaking

Shekhar, Sudip; Li, X.; Allstot, D.J.

doi:10.1109/rfic.2006.1651088

Cited by 26 publications

(32 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the NF of the CG LNA is considerably larger than that of the CMOS common-source or cascode LNAs. Previously employed in common-source LNAs in [5] and [6], the -boosting technique was proposed by [7] to improve the NF performance of a UWB CG LNA. On the other hand, recent advances in high-speed integrated circuits and continuous scaling of minimum feature sizes of silicon-based devices have increased the interest in on-chip implementation of transmission lines (TLs), which are key components of broadband distributed circuits.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

Heydari

2007

IEEE J. Solid-State Circuits

127

View full text Add to dashboard Cite

In this paper, the systematic design and analysis of a CMOS performance-optimized distributed low-noise amplifier (DLNA) comprising bandwidth-enhanced cascode cells will be presented. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the bandwidth, while reducing the high-frequency input-referred noise. The noise analysis and optimization of the DLNA accurately accounts for the impact of thermal noise of line terminations and all device noise sources of each CMOS cascode cell including flicker noise, correlated gate-induced noise and channel thermal noise on the overall noise figure. A three-stage performance-optimized wideband DLNA has been designed and fabricated in a 0.18-m SiGe process, where only MOS transistors were utilized. Measurements of the test chip show a flat noise figure of 2.9 dB, a forward gain of 8 dB, and input and output return losses below 12 dB and 10 dB, respectively, across the 7.5 GHz UWB band. The circuit exhibits an average IIP3 of 3.55 dBm. The 872 m 872 m DLNA chip consumes 12 mA of current from a 1.8-V DC voltage.

show abstract

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

Heydari

2007

IEEE J. Solid-State Circuits

127

View full text Add to dashboard Cite

show abstract

“…In terms of bandwidth this topology covers the frequency range from 1 GHz to 10.5 GHz, similar to the other works. Considering [3] and [7], whereas some other topologies do not indicate these charcteristic at all. The power dissipation of 36 mW is relatively high compared, but offers still a manageable value for wireless devices, which can be further reduced when substituting the current consuming differential pair by an alternative stage, e.g.…”

Section: Discussionmentioning

confidence: 99%

“…The drawback of this kind of topology, based on a common source amplifier with inductive degeneration, is the large occupied chip area, due to the huge number of passive coils needed. Another topology that offers wideband input match is the common gate amplifier [3], [4], also being able to apply so called noise cancelling [5]. The problem with this topology is the relatively high value for the minimum achievable noise figure.…”

Section: Introductionmentioning

confidence: 99%

Inductorless 1–10.5 GHz wideband LNA for multistandard applications

Hampel

Schmitz

Tiebout

et al. 2009

2009 IEEE Asian Solid-State Circuits Conference

View full text Add to dashboard Cite

This article presents the design of a fully integrated inductorless LNA for wireless applications including WLAN, Bluetooth and UWB. The circuit was fabricated in 65nm CMOS technology and operates at a supply voltage of 1.2 V. The twostage design is comprised of a current reuse shunt feedback input stage followed by a differential pair, incorporating an active inductor load to compensate the gain roll-off. The circuit exhibits a peak gain of 16.5 dB, while the 3-dB bandwidth as well as the input and output matching of better than -10 dB range from 1-10.5 GHz. The noise figure is kept below 5 dB within this frequency range, offering a minimum noise figure of 3.9 dB. The linearity in terms of P 1dB,out and oIP3 offers nearly constant behavior with -5 dBm and 3 dBm respectively. The active area takes up only 0.021 mm 2 .

show abstract

“…Because of the corresponding gain, performance is usually not high enough for UWB application due to the tradeoff between gain and bandwidth [15,16]. The presented LNA adopts two-stage cascade architecture to achieve enough power gain and bandwidth.…”

Section: Gain Analysis (Compensation)mentioning

confidence: 99%

Design of Low Power CMOS LNA with Current-Reused and Notch Filter Topology for DS-UWB Application

Hsu¹,

Du²,

Chiu³

2012

WET

View full text Add to dashboard Cite

This paper presents the design of a low power LNA with second stage that uses a notch filter for DS-UWB application. The LNA employs a current reuse structure to reduce the power consumption and an active second order notch filter to produce band rejection in the 5 -6 GHz frequency band. The input reflection coefficient S11 and output reflection S22 are both less than -10 dB. The maximum power gain S21 is 15 dB while the maximum rejection ratio is over -10 dB at 4.8 GHz. The minimum noise figure is 5 dB. The input referred third-order intercept point (IIP3) is -7 dBm at 6 GHz. The power consumption is 6.4 mW from a 1-V power supply.

show abstract

A CMOS 3.1-10.6GHz UWB LNA Employing StaggerCompensated Series Peaking

Cited by 26 publications

References 6 publications

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

Inductorless 1–10.5 GHz wideband LNA for multistandard applications

Design of Low Power CMOS LNA with Current-Reused and Notch Filter Topology for DS-UWB Application

Contact Info

Product

Resources

About

A CMOS 3.1-10.6GHz UWB LNA Employing StaggerCompensated Series Peaking

Cited by 26 publications

References 6 publications

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

Inductorless 1&#x2013;10.5 GHz wideband LNA for multistandard applications

Design of Low Power CMOS LNA with Current-Reused and Notch Filter Topology for DS-UWB Application

Contact Info

Product

Resources

About

Inductorless 1–10.5 GHz wideband LNA for multistandard applications