A CMOS general-purpose sampled-data analog processing element

Dudek, Piotr; Hicks, Peter

doi:10.1109/82.842115

Cited by 26 publications

(20 citation statements)

References 30 publications

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“…The possible architectures and circuit solutions can be greatly simplified because the primary application of the sensor is monitoring and controlling of objects, which can be done based on low or medium image resolutions and dynamics. Typically, accuracy of image signal processing equivalent to 5 or 6 bits resolution is sufficient [10] for satisfactory results. The relatively low accuracy of such systems allows application of analogue signal processing, which contrary to digital one, enables greater reduction of power consumption and a chip area.…”

Section: Architecture Of a Vision Chipmentioning

confidence: 99%

CMOS realisation of analogue processor for early vision processing

Jendernalik¹,

Jakusz²,

Blakiewicz³

et al. 2011

Bulletin of the Polish Academy of Sciences: Technical Sciences

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Abstract. The architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms is presented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated using a 0.35 µm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 frames per second, or achieve very low power consumption, several µW. Finally, the experimental results are presented and discussed.

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Section: Architecture Of a Vision Chipmentioning

confidence: 99%

CMOS realisation of analogue processor for early vision processing

Jendernalik¹,

Jakusz²,

Blakiewicz³

et al. 2011

Bulletin of the Polish Academy of Sciences: Technical Sciences

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“…A subsequent fabrication of a larger array is planned. The SCAMP approach is computationally very efficient, in terms of performance/area and performance/power dissipation [8]. The performance figures of merit for this implementation are expected to surpass the previous implementation and will be reported at a later date (the experimental results should be available by May 2003).…”

Section: Implementation and Conclusionmentioning

confidence: 99%

“…A single controller issues instructions, which are broadcast to each PE in the array, and the PEs execute instructions in parallel, each operating on their local data. While the architecture and the functionality of the PEs is similar to that of digital processors, they represent data using analogue sampled signals and process data using analogue circuits, and are thus called Analogue Processing Elelments (APEs) [8]. The overall block diagram of the system is shown in Fig.1 The design of the APE in the SCAMP-2 chip is based on switchedcurrent techniques and is similar to the one reported in [4], although several circuit improvements have been introduced to reduce power dissipation, improve matching and reduce errors associated with analogue signal processing.…”

Section: Scamp-2 Chipmentioning

confidence: 99%

“…reset of photodetectors). The arithmetic operations of addition, inversion, and division are executed exploiting computational capabilities inherent in the design of switched-current registers and no additional hardware is required for this purpose [8], which is one of the reasons for high efficiency and small silicon area of the "analogue microprocessor" approach. It should be noted that the previous SCAMP implementation contained an explicit current multiplier.…”

Section: Scamp-2 Chipmentioning

confidence: 99%

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A flexible global readout architecture for an analogue SIMD vision chip

Dudek

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

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A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architecture. A combination of the addressing flexibility provided by the novel readout scheme and the global operation capability of the analogue processors results in the increased functionality of the smart sensor device. Example applications of the proposed architecture are discussed. In addition to low-level image processing algorithms, such as filtering or edge detection, which are efficiently executed on a nearest-neighbour connected fine-grain massively parallel SIMD array, it is also possible to implement global algorithms, such as histogramming. The proposed architecture enables increased control over wave-propagation-type algorithms and simplifies the design of winner-take-all algorithms. Significant speed-up can be achieved in applications such as visual tracking.

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“…Therefore, the chip should be particularly suited to lowpower requirements of battery-powered systems. The APEs are implemented as "analogue microprocessors" [1], they execute software instructions, but achieve this using analogue circuits, and store data in a form of analogue sampled signals. Switched-current signal processing techniques are employed to achieve "ALU-free" design, i.e.…”

Section: Methodsmentioning

confidence: 99%

Implementation of SIMD Vision Chip with 128X128 Array of Analogue Processing Elements

Dudek

2005 IEEE International Symposium on Circuits and Systems

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This paper presents the latest implementation of the SIMD Current-mode Analogue Matrix Processor architecture. The SCAMP-3 vision chip has been fabricated in a 0.35µm CMOS technology and comprises a 128×128 general-purpose programmable processor-perpixel array. The architecture of the chip is overviewed and implementation issues are considered. The circuit design of the analogue register is presented, the layout of the Analogue Processing Element is discussed and the design of control-signal drivers and readout circuitry is overviewed. INTRODUCTIONProgrammable vision chips, which combine image sensors and pixel-parallel processors, can offer significant advantages in many computer vision applications, providing image pre-processing capability with low power consumption and high computational performance. Inherently parallel low-level image processing algorithms map naturally to fine-grained pixel-parallel processor arrays, while the ability to perform computations right next to the sensors reduces the power consumption and I/O bandwidth requirements. However, the requirement of physically co-locating photosensor array and processor array, in a processor-perpixel manner, introduces severe constraints in terms of the physical design of the device, circuit area, and power consumption. This is especially true if a low-cost requirement implies the use of a standard CMOS technology. To meet the implementation constraints, mixed-mode and analogue circuits are usually employed in the design of the processor. It has been demonstrated [1-3] that use of analogue processors can offer significant benefits in terms of cost, processing speed and power consumption, when limited accuracy of processing is acceptable. The implementation of a large analogue VLSI circuit, however, is a challenging task. The trade-offs between cell area, power dissipation and processing speed have to be suitably resolved. A full-custom design is obviously required, and the constraints on the physical geometry of the circuit topology are an important consideration affecting the circuit and system design. This implies a co-design of processor architecture, circuitry and layout. Furthermore, to achieve a robust implementation, the issues of noise and mismatch have to be carefully controlled. Again, the architecture and physical design have to be considered together.In this paper the design of a 128×128 pixel-perprocessor vision chip (SCAMP-3, shown in Figure 1) is presented. The chip has been fabricated in a 0.35µm CMOS technology and comprises over 1.8 million transistors (most of which are working in analogue mode). The design is based on the design used in our previous 39×48 array chip, which has been reported in [4]. Some details of the processing element design and readout architecture were presented in [5] and [6]. In this paper, several aspects of the chip implementation are elaborated. In particular, detailed schematic diagram of the analogue register circuit is presented, the layout of the processing element is discussed and the control...

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A CMOS general-purpose sampled-data analog processing element

Cited by 26 publications

References 30 publications

CMOS realisation of analogue processor for early vision processing

CMOS realisation of analogue processor for early vision processing

A flexible global readout architecture for an analogue SIMD vision chip

Implementation of SIMD Vision Chip with 128X128 Array of Analogue Processing Elements

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