A CMOS low-power ADC for DVB-T and DVB-H systems

Adeniran, O.A.; Demosthenous, Andreas; Clifton, Chris; Atungsiri, S.A.; Soin, Randeep Singh

doi:10.1109/iscas.2004.1328168

Cited by 14 publications

(9 citation statements)

References 5 publications

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“…Moreover, the hardware cost of ADC increases significantly with sample rate. Since the commercial available digital demodulators utilize a 20.48 MHz crystal clock [15], the use of the processor operated at 25 MHz has a much lower ADC sample rate than that operated at 40 MHz.…”

Section: Design Requirement For Dvb-t2 Systemmentioning

confidence: 99%

Low-cost FFT processor for DVB-T2 applications

Lin

Wey

Shieh

2010

IEEE Trans. Consumer Electron.

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An efficient Fast Fourier Transform (FFT) processor is greatly needed for real-time operation in many OFDM applications, such as xDSL, DAB, DVB-T/H, and etc. This paper presents a low-cost Parallel Memory-based FFT (PMB-FFT) processor for DVB-T2 applications. The processor has been designed and implemented in 90nm 1P9M CMOS process. Experimental results show that the PMB-FFT processor meets the DVB-T2 standard with N=32,768 points, and takes only 2.51 mm 2 in the core area with a power consumption of 0.89 mW at 25MHz.

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Section: Design Requirement For Dvb-t2 Systemmentioning

confidence: 99%

Low-cost FFT processor for DVB-T2 applications

Lin

Wey

Shieh

2010

IEEE Trans. Consumer Electron.

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“…Among various ADC architectures, pipelined ADCs have proven to be very efficient architectures for meeting the low power dissipation, medium resolution and high input bandwidth requirements [1]- [8], [10]- [16], [18], [25]- [29].…”

Section: Adc Architecturementioning

confidence: 99%

“…Many of the applications such as battery-powered portable devices also require low power consumption. For example, in the digital video broadcasting over terrestrial (DVB-T) and handheld (DVB-H) systems, a low-power 10-bit ADC that runs at tens of mega hertz clock frequency and can deliver the required performance in a direct IF (intermediate frequency) sampling architecture is required [1]. Thus, optimized implementations of low-power ADCs play an important role when high-performances are targeted.…”

Section: Introductionmentioning

confidence: 99%

A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications

Zeng

Xie

et al. 2008

IEEE J. Solid-State Circuits

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This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter (ADC) that is implemented in a 0.18 m CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which additional switches are introduced to reduce the crosstalk between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths. A symmetrical gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.57 least significant bit (LSB) and 0.8 LSB, respectively, at full sampling rate. The ADC exhibits higher than 9.1 effective number of bits (ENOB) for input frequencies up to 30 MHz, which is the twofold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 21.6 mW from a 1.8-V power supply and occupies 0.7 mm 2 , which also includes the bandgap and buffer amplifiers. The figure-of-merit (FOM) of this ADC is 0.26 pJ/step.

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“…have created the demand for power-efficient ADCs with resolutions of 8-10 bits and sampling speeds of several tens of MS/s [2,67]. Medium-resolution, high-speed analog-to-digital conversion has traditionally been dominated by pipelined ADCs.…”

Section: Introductionmentioning

confidence: 99%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At V DD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm 2 .The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-tohigh sampling rates, the DAC reference settling poses a speed bottleneck in chargeredistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well iv critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the ...

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A CMOS low-power ADC for DVB-T and DVB-H systems

Cited by 14 publications

References 5 publications

Low-cost FFT processor for DVB-T2 applications

Low-cost FFT processor for DVB-T2 applications

A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

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