A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications

Abstract

This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter (ADC) that is implemented in a 0.18 m CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which additional switches are introduced to reduce the crosstalk between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths. A symmetrical gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.57 least significant bit (LSB) and 0.8 LSB, respectively, at full sampling rate. The ADC exhibits higher than 9.1 effective number of bits (ENOB) for input frequencies up to 30 MHz, which is the twofold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 21.6 mW from a 1.8-V power supply and occupies 0.7 mm 2 , which also includes the bandgap and buffer amplifiers. The figure-of-merit (FOM) of this ADC is 0.26 pJ/step.

RF and mixed signal circuits for a DVB-H receiver

“…20). Among many ADC architectures, pipeline converters have proven to be a very efficient architecture for meeting the low power consumption and high input bandwidth requirements of DVB-H standard [17,18]. Moreover, the evolution of CMOS technology has made the choice of a continuous-time Sigma-Delta (RD) architecture very attractive because its power efficiency.…”

A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC

“…Complex calibration schemes and/or circuit techniques [4][5][6][7][8], which are usually needed to enhance the linearity and/or correct the mismatches such as compensating low gain, low bandwidth and incomplete settling of opamps, need complicated algorithm, additional digital circuitry and extra calibration cycles. SHA-less and opamp-sharing are two important ways for low-power pipelined ADC design [9][10][11][12][13]. However, they also bring some drawbacks affecting the ADC performance, such as nonlinearity and distortion.…”

“…Reference [10] is also without opamp-sharing and use traditional simple 1.5b/stage architecture when utilizing SHA-less. the proposed structure in [11] may not be suitable for the ADCs that are expected to run at the maximum achievable sampling rate for a given resolution and technology, Because the opamp used in the proposed first stage needs to be faster, simultaneously meaning more power consumption, than the one in the traditional first stage. The proposed structures in [12,13], taking use of some techniques proposed in [14], need additional clocks of different duty cycle.…”

Switch-embedded opamp-sharing MDAC with dual-input OTA in pipelined ADC

“…To alleviate the non-resetting problem, feedback signal polarity inverting (FSPI) is used to alternate the signal polarity, but it can only reduce the opamp offset by 2/3 [2]. To break the crosstalk path, isolation switches are added to tie the parasitic capacitor to ground, and the signal-to-noise-and-distortion ratio (SNDR) is improved by 1-2 dB, but the added switches increase the series resistances and the charge injection [3]. Although opamp current reuse can solve the problems of non-resetting and the crosstalk path by using both NMOS and PMOS input differential pairs in shared opamps, the capacitive level shifter increases the design complexity and the PMOS input differential pair decreases the power efficiency [4].…”

“…Fig. 4 shows the measured SNDR and SFDR compared between this work and a traditional ADC with the additional isolated switches as in [3], and the two ADCs are the same except the shared method of opamp. A performance summary is shown in Table 1.…”