Switch-embedded opamp-sharing MDAC with dual-input OTA in pipelined ADC

Abstract

A switch-embedded opamp-sharing multiplying digital-to-analogue converter (MDAC) with dual-input-differential-pair operational transconductance amplifier (OTA) is proposed to eliminate the non-resetting and successive-stage crosstalk problems in the conventional opampsharing technique. A 10-bit 80 MS/s pipelined analogue-to-digital converter (ADC) is implemented in a 0.18 mm CMOS process by using the proposed MDAC. Compared with a traditional opampsharing ADC, the measured signal-to-noise ratio is improved from 55.9 to 60.1 dB and the spurious free dynamic range is improved from 66 to 76 dB without any additional power or area consumption or clock phase.Introduction: Applications used in many electronic systems, such as video decoder and wireless communication, require high-resolution low-power analogue-to-digital converters (ADCs). One of the most efficient ways to save power is opamp-sharing between successive pipelined stages. However, that is achieved at the cost of resolution reduction, since the opamp-sharing ADC has two serious problems. First, because the opamp input summing node is never reset, every input sample will be affected by the error voltage stored on the input capacitor due to the previous sample. Thus it suffers from the memory effect, which can be considered as a kind of offset [1]. Secondly, there is a potential crosstalk path between two successive stages caused by the parasitic capacitors of switches that are used to implement opamp sharing. The signals in the current and successive stages, which appear at input nodes of the shared opamp, will influence each other through the crosstalk path. In addition, the opamp-sharing switches also introduce charge injection and input-dependent resistances. These factors deteriorate both the signal-to-noise ratio (SNR) and the linearity. To alleviate the non-resetting problem, feedback signal polarity inverting (FSPI) is used to alternate the signal polarity, but it can only reduce the opamp offset by 2/3 [2]. To break the crosstalk path, isolation switches are added to tie the parasitic capacitor to ground, and the signal-to-noise-and-distortion ratio (SNDR) is improved by 1-2 dB, but the added switches increase the series resistances and the charge injection [3]. Although opamp current reuse can solve the problems of non-resetting and the crosstalk path by using both NMOS and PMOS input differential pairs in shared opamps, the capacitive level shifter increases the design complexity and the PMOS input differential pair decreases the power efficiency [4].

A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC

“…This enables the FADAC obtaining much time margin and being tolerant to the slewing during the opamp settling in the hold phase. The summing node reset problem in conventional opamp-sharing structure is mitigated by utilizing dual-input differential pairs in the amplifier [17], which is shown in Figure 4.…”

“…This paper presents the realization of a low-voltage 0.13-µm CMOS, 12-bit, 20 MS/s ADC. The proposed FADAC is incorporated into a SHA-less and opamp-sharing pipelined architecture [15][16][17][18]. A simple digital foreground calibration is applied to compensate the carry transition error of the 1-bit FADAC [19][20][21].…”

A highly linear 1.2 V 12bit 5–45 MS/s CMOS pipelined ADC with CM-sensing-and-input-interchanged OTA sharing

“…While one input pair is utilized for amplification, the other input pair is reset. Switchembedded opamp-sharing described in [5] switches the OTA tail current between two NMOS differential input pairs, and utilizes a special two-phase overlapped clock to shorten the settling time. Current reuse OTA described in [1] has cascaded Y. Qin (&) Á Q. Chen Á Z. Hong State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China e-mail: yajieqin@fudan.edu.cn dual NMOS differential input pairs and maximizes the power savings from reusing current.…”

A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture

“…Many applications such as video detector and wireless communication systems, require high speed, low power, and high resolution analog-to-digital converters(ADCs) [1]. Since the required accuracy gradually decreases in the later stages of the pipeline architecture, the power consumption can be reduced by properly scaling the capacitor sizes and opamp transistors sizes (w/l) and bias current, without degrading the resolution of the ADC.…”