A co-design approach for embedded system modeling and code generation with UML and MARTE

Vidal, Jorgiano; Lamotte, Florent de; Gogniat, Guy; Soulard, Philippe; Diguet, Jean-Philippe

doi:10.1109/date.2009.5090662

Cited by 95 publications

(69 citation statements)

References 6 publications

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“…The MoPCoM project [8] aims to target modeling and code generation of dynamically reconfigurable embedded systems using the MARTE profile [9]. While the authors claim that they are capable of creating a complete SoC Co-Design framework, in reality, only the high level application model is converted into an equivalent hardware design, with each application task transformed into a hardware accelerator in a target FPGA.…”

Section: Related Workmentioning

confidence: 99%

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Quadri

Meftali

Dekeyser

2010

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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Abstract-Due to continuous hardware/software evolution related to Systems-on-Chip (SoC) and the addition of features such as Partial Dynamic Reconfiguration, the complexity of SoC design and development has escalated exponentially. This has resulted in increased time to market and development costs. Without the usage of effective design tools and methodologies, large complex SoCs are becoming increasingly difficult to manage, resulting in a productivity gap. The design space, representing all technical decisions that need to be elaborated by the SoC design team is therefore, becoming immense and difficult to explore. Similarly, manipulation of these systems at low implementation levels such as Register Transfer Level (RTL) can be hindered by human interventions and the subsequent errors. This paper presents a novel design methodology that decreases the design complexity by raising the design abstraction levels. It makes use of ModelDriven Engineering and the UML MARTE profile to move from high level UML models to automatic code generation, for implementing dynamically reconfigurable SoCs.

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Section: Related Workmentioning

confidence: 99%

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Quadri

Meftali

Dekeyser

2010

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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“…An initial approach has been presented in [16], inspired from several initial works such as illustrated in [17]. However, the authors are only able to generate a textual description related to the hardware components in the modeled FPGA, which is taken as input by the FPGA tools for eventual manual manipulation.…”

Section: Related Workmentioning

confidence: 99%

Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis

Cherif

Quadri

Meftali

et al. 2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Abstract-Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible nature. However due to the tremendous amount of hardware resources available in these systems, new design methodologies and tools are required to reduce their design complexity. In this paper we present an exploratory analysis for specification of these systems, while utilizing the UML MARTE (Modeling and Analysis of Real-time and Embedded Systems) profile. Our contributions permit us to model fine grain reconfigurable FPGA based SoC architectures while extending the profile to integrate new features such as Partial Dynamic Reconfiguration supported by these modern systems. Finally we present the current limitations of the MARTE profile and ask some open questions regarding how these high level models can be effectively used as input for commercial FPGA simulation and synthesis tools. Solutions to these questions can help in creating a design flow from high level models to synthesis, placement and execution of these reconfigurable SoCs.

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“…In [11], the authors presented a UML/SystemC profile for SystemC code generation from UML structural and Statecharts diagrams. In [12], the authors proposed a UML/MDA approach called MoPCoM methodology that permits automatic SystemC and VHDL code generation from UML models and MARTE profile by means of MDA techniques. Input models are focused on UML class, component, and Statecharts diagrams.…”

Section: Related Workmentioning

confidence: 99%

Automatic SystemC Code Generation from UML Models at Early Stages of Systems on Chip Design

Boutekkouk¹

2010

IJCA

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In this paper, we present our approach for automatic SystemC code generation from UML models at early stages of Systems On Chip (SOC) design. A particularity of our proposed approach is the fact that SystemC code generation process is performed through two levels of abstraction. In the first level, we use UML hierarchic sequence diagrams to generate a SystemC code that targets algorithmic space exploration and simulation. In the second level of abstraction, messages that occur in sequence diagrams are implemented using UML activity diagrams whose actions are expressed in the C++ Action Language (AL) included in the Rhapsody environment from which a full SystemC code is generated for both simulation and synthesis. General TermsSystems On Chip, System Modeling

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A co-design approach for embedded system modeling and code generation with UML and MARTE

Cited by 95 publications

References 6 publications

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis

Automatic SystemC Code Generation from UML Models at Early Stages of Systems on Chip Design

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