A coefficient segmentation algorithm for low power implementation of FIR filters

Abstract

The authors present a multiplication algorithm for low power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual coefficients into two primitive sub-components. The decomposition, performed using a heuristic approach, divides a given coefficient such that a part is produced which can be implemented using a single shift operation leaving another part with a reduced wordlength to be applied to the coefficient input of the hardware multiplier. This results in a significant reduction in the amount of switched capacitance and consequently power consumption. The algorithm has been used with a number of practical FIR filter examples achieving up to 63% saving in power. Results are provided which illustrate the effect of the algorithm on the amount of switched capacitance for different size multipliers. The paper provides a description of the algorithm, the evaluation procedure used, and associated results including overheads due to shift operations.

Design of low power multimode time-shared filters

“…Most of the design strategies directed at minimizing the power consumption of time-shared filters like coefficient reordering [4], low power folding [5] and data block processing [6] have typically focused on minimizing the switched capacitance, by increasing the temporal correlation of the multiplier inputs. The coefficient segmentation [7] approach minimizes the effective switched capacitance by splitting the coefficients into subcomponents that result in lower switching activity.…”

Sign Bit Reduction Encoding For Low Power Applications

“…Two's complement (2'sc) number representation is the most commonly used encoding scheme in DSP applications [1]. This is due to ease of performing arithmetic operations such as additions and subtractions with 2'sc numbers [1].…”

“…A major drawback of this representation is the sign extension bits (MSB sign bits). When a 2'sc number changes its sign, these bits switch from 0 to 1 or 1 to 0 which could cause a large power consumption [1]. Several data representations have been suggested to reduce the power consumption in multipliers and adders (see e.g., [2,3]).…”

“…2'sc number representation is the most commonly used encoding scheme in DSP applications [1]. An N-bit 2'sc number is represented by N bits as…”

Low power, flexible FIR filters in the digital frontend of green radios

“…The regularity of FIR filter data flow graphs allows variable filter lengths to be folded onto a fixed set of multiply and accumulate (MAC) units, with minimal changes to the control logic. Prior works on reducing the power consumption of time-shared FIR filters have usually focused on reducing the increased switching activity due to loss of input correlation in temporal style implementations [13][14][15]. In the nanoscale CMOS technologies, the leakage component dominates the overall power consumption [16].…”