A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

Abstract

In this paper, we evidence the link between the planar and cylindrical junctionless field effect transistors (JL-FETs) from the electrostatics and current point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for JL nanowires can be mapped on the planar doublegate topology generating only negligible mismatch, meaning that both devices can share the same core model as far as long channels are considered. These preliminary results are a first step toward a unification of compact models for JL-FETs.Index Terms-Double gate (DG), enhancement mode, field effect transistor (FET), junctionless, modeling, nanowires (NWs).

Modeling Channel Thermal Noise and Induced Gate Noise in Junctionless FETs

“…These noise models represent the first step toward compact modeling of thermal noise in JL FETs devices. In addition, based on the equivalence between planar and cylindrical JL FETs [10], we expect that such a model could also be appropriate for JL NW.…”

“…Note that when the whole channel operates in depletion, Y FB = 0 is imposed in (7)- (10). Similarly, when the whole channel is in accumulation, Y FB = L G holds in (3)-(6).…”

“…Although there have been quite a lot of efforts to model the dc characteristics of JL devices [4]- [10], not so much interest has been paid to ac modeling [11]- [13], and even less for thermal noise, despite its relevance for RF design. Some investigations have been carried out for low-frequency noise by means of Synopsys technology computer-aided design (TCAD) simulations and experimental results [13]- [16], but there is still no explicit thermal noise model for this device, and no assessment against the regular inversion mode (IM) FET counterpart.…”

A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure

“…To understand this different conduction mechanism analytically, several models have been introduced for double-gate junctionless transistors (DGJL-FETs). Current-voltage models have been introduced [6], [7] and analytical threshold voltage models have been developed [8]- [10] for symmetric DGJL-FETs. However, a general potential model represented with analytic formulas for tied and untied DGJL-FETs with corresponding symmetric and asymmetric structures has not yet been developed.…”

“…Device simulations are conducted with the aid of the SILVACO 2-D simulator using the Lombardi mobility model along with Shockley-Read-Hall and Fermi-Dirac carrier statistics [13]. We neglect quantum mechanical effects because the simulated channel is thicker than 10 nm in the doping concentration of 1 × 10 19 cm −3 or less [7], [8]. In addition, we also ignore the parasitic series resistance arisen from the S/D extension in order to simplify the model.…”