2014
DOI: 10.4304/jcp.9.11.2552-2558
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A Communication-aware Scheduling Algorithm for Hardware Task Scheduling Model on FPGA-based Reconfigurable Systems

Abstract: Task scheduling is an important aspect of high performance reconfigurable computing. Most of the heuristics for this NP-hard problem are based on a simple abstract model of FPGA and have little investigation into optimizing data communication which influences the system performance importantly. To solve this problem, a Communication-aware Maximum Adjacent Edges (CA-MAE) algorithm based on new 2D reconfigurable model is proposed, which could reduce communication distance during scheduling and enhance the system… Show more

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Cited by 3 publications
(5 citation statements)
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“…However, this method does not consider FPGA on‐chip interconnect resources. CA‐MAE [ 34 ] considers the actual communication channel, local bus, system bus, and peripheral bus of FPGA, as shown in Fig 7…”
Section: Fpga‐based Hardware Task Scheduling Methodsmentioning
confidence: 99%
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“…However, this method does not consider FPGA on‐chip interconnect resources. CA‐MAE [ 34 ] considers the actual communication channel, local bus, system bus, and peripheral bus of FPGA, as shown in Fig 7…”
Section: Fpga‐based Hardware Task Scheduling Methodsmentioning
confidence: 99%
“…[29,30] Additional communication constraints Refs. [33,34] Task proximity placement Refs. [35,36] Task grouping and clustering…”
Section: Table 2 Summary Of Implementation Methodsmentioning
confidence: 99%
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