A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS

Lu, Minyi; Fan, Ao; Xu, Jiaming; Shan, Weiwei

doi:10.1109/trustcom/bigdatase.2018.00204

Cited by 16 publications

(8 citation statements)

References 17 publications

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“…Table 4 shows the comparison with the existing state of the art, from which we can see that when comparing the single AES core, the implementation that goes the small-area route [27,32] has lower power consumption and significantly insufficient throughput. However, in terms of energy efficiency, the proposed design yields performance close to [27]. Compared with [23], which has the same processing speed, our proposal is almost the same in terms of area and better in energy efficiency.…”

Section: Experimental Results and Analysismentioning

confidence: 99%

“…e AES structure proposed in [26] is composed of 4 shared S-Boxes, which are used alternately by key expansion and round function for 1 and 4 clock cycles, respectively (see Figure 5(a)). To implement an ultimate small-area circuit, a team from Southeast University [27] proposed a single S-Box structure, which requires 20 cycles to complete a SubBytes step (see Figure 5(b)).…”

Section: Related Workmentioning

confidence: 99%

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A Lightweight AES Coprocessor Based on RISC-V Custom Instructions

Pan

Liu

et al. 2021

Security and Communication Networks

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With the increasing popularity of the Internet of Things (IoT), the issue of its information security has drawn more and more attention. To overcome the resource constraint barrier for secure and reliable data transmission on the widely used IoT devices such as wireless sensor network (WSN) nodes, many researcher studies consider hardware acceleration of traditional cryptographic algorithms as one of the effective methods. Meanwhile, as one of the current research topics in the reduced instruction set computer (RISC), RISC-V provides a solid foundation for implementing domain-specific architecture (DSA). To this end, we propose an extended instruction scheme for the advanced encryption standard (AES) based on RISC-V custom instructions and present a coprocessor designed on the open-source core Hummingbird E203. The AES coprocessor uses direct memory access channels to achieve parallel data access and processing, which provides flexibility in memory space allocation and improves the efficiency of cryptographic components. Applications with embedded AES custom instructions running on an experimental prototype of the field-programmable gate array (FPGA) platform demonstrated a 25.3% to 37.9% improvement in running time over previous similar works when processing no less than 80 bytes of data. In addition, the application-specific integrated circuit (ASIC) experiments show that in most cases, the coprocessor only consumes up to 20% more power than the necessary AES operations.

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Section: Experimental Results and Analysismentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A Lightweight AES Coprocessor Based on RISC-V Custom Instructions

Pan

Liu

et al. 2021

Security and Communication Networks

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“…In this set of experiments, the proposed block coding based IPD channel is compared against several methods for secure data transmission, including (1) thermal covert channel (TCC) [20], [35]- [37], (2) cache covert channel [30]- [32], and (3) hardware-based encryption [33].…”

Section: F Comparison With Other Secured Transmission Methodsmentioning

confidence: 99%

“…Compared with the proposed block coding based IPD channel, the hardware-based encryption scheme (e.g., AES) encrypts data before secure transmission, which can achieve a PER of 0.03% [51], but it requires additional hardware circuit for AES coding and decoding. As reported from [33], the AES encoder circuit using 28nm TSMC technology has an area of 0.0028 mm 2 and consumes 48 mJ when encrypting 1000 bits. As a comparison, the block coding based IPD channel requires no additional circuit, and its energy consumption is only 7.5% of the encryption scheme.…”

Section: F Comparison With Other Secured Transmission Methodsmentioning

confidence: 99%

Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays

Wang

Jiang

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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As the network-on-chip (NoC) integrated into an SoC design can come from an untrusted third party, there is a growing risk that data integrity and security get compromised when supposedly sensitive data flows through such an untrusted NoC. We thus introduce a new method that can ensure secure and secret data transmission over such an untrusted NoC. Essentially, the proposed scheme relies on encoding binary data as delays between packets travelling across the source and destination pair. The maximum data transmission rate of this inter-packet-delay (IPD) based communication channel can be determined from the analytical model developed in this paper. To further improve the undetectability and robustness of the proposed data transmission scheme, a new block coding method and communication protocol are also proposed. Experimental results show that the proposed IPD-based method can achieve a packet error rate (PER) of as low as 0.3% and an effective throughput of 2.3 × 10 5 bps, outperforming the methods of thermal covert channel, cache covert channel, and circuit-based encryption, and thus is suitable for secure data transmission in unsecure systems.

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“…On top of being the most well-studied block cipher algorithm (Dutta, Ghosh and Bayoumi, 2019), this algorithm continues to the be subject of further studying past, present, and future optimizing its applicability for today's needs based on the intensely growing environmental demands in every single aspect of modern life with an ultimate goal of achieving sustainability. Moreover, it is through reducing the consumption of power and energy, a compact AES circuit design was proposed by Lu, et al, 2018. Only one S-Box is used in the cipher design, this one S-Box is utilized in key expansion process and data encryption process. This reduction in components achieves less latency in encryption process; and small area with high energy and throughput as a circuit design.…”

Section: Lightweight Advanced Encryption Standard (Aes)mentioning

confidence: 99%

Modern and Lightweight Component-based Symmetric Cipher Algorithms

Qassir

Gaata

Sadiq

2022

ARO

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Information security, being one of the corner stones of network and communication technology, has been evolving tremendously to cope with the parallel evolution of network security threats. Hence, cipher algorithms in the core of the information security process have more crucial role to play here, with continuous need for new and unorthodox designs to meet the increasing complexity of the applications environment that keep offering challenges to the current existing cipher algorithms. The aim of this review is to present symmetric cipher main components, the modern and lightweight symmetric cipher algorithms design based on the components that utilized in cipher design, highlighting the effect of each component and the essential component among them, how the modern cipher has modified to lightweight cipher by reducing the number and size of these components, clarify how these components give the strength for symmetric cipher versus asymmetric of cipher. Moreover, a new classification of cryptography algorithms to four categories based on four factors is presented. Finally, some modern and lightweight symmetric cipher algorithms are selected, presented with a comparison between them according to their components by taking into considerations the components impact on security, performance, and resource requirements.

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A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS

Cited by 16 publications

References 17 publications

A Lightweight AES Coprocessor Based on RISC-V Custom Instructions

A Lightweight AES Coprocessor Based on RISC-V Custom Instructions

Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays

Modern and Lightweight Component-based Symmetric Cipher Algorithms

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