A Lightweight AES Coprocessor Based on RISC-V Custom Instructions

Abstract

With the increasing popularity of the Internet of Things (IoT), the issue of its information security has drawn more and more attention. To overcome the resource constraint barrier for secure and reliable data transmission on the widely used IoT devices such as wireless sensor network (WSN) nodes, many researcher studies consider hardware acceleration of traditional cryptographic algorithms as one of the effective methods. Meanwhile, as one of the current research topics in the reduced instruction set computer (RISC), RISC-V provides a solid foundation for implementing domain-specific architecture (DSA). To this end, we propose an extended instruction scheme for the advanced encryption standard (AES) based on RISC-V custom instructions and present a coprocessor designed on the open-source core Hummingbird E203. The AES coprocessor uses direct memory access channels to achieve parallel data access and processing, which provides flexibility in memory space allocation and improves the efficiency of cryptographic components. Applications with embedded AES custom instructions running on an experimental prototype of the field-programmable gate array (FPGA) platform demonstrated a 25.3% to 37.9% improvement in running time over previous similar works when processing no less than 80 bytes of data. In addition, the application-specific integrated circuit (ASIC) experiments show that in most cases, the coprocessor only consumes up to 20% more power than the necessary AES operations.

FAC-V: An FPGA-Based AES Coprocessor for RISC-V

“…As the RISC-V has grown in popularity, several domain-specific coprocessor units have been implemented, and the first steps toward making an AES coprocessor, both in Application-Specific Integrated Circuit (ASIC) [30][31][32][33][34][35] or FPGA technologies [36][37][38], have already been taken. Table 1 shows a comparison among different state-of-the-art AES implementations according to the year, the technology, the type of architecture, the frequency, the number of clock cycles required per encryption, and the throughput.…”

Tracking accelerator based on RISC-V custom instructions for GNSS receiver

“…RISC-V Instruction Set Architecture (ISA) has grown rapidly in recent years. It has been widely used in various fields such as the Internet of Things, cryptography algorithms, machine learning, and digital signal processing [9,10,11,12,13,14]. GNSS receivers using RISC-V processors are also gradually emerging.…”

An Optimized Implementation of Activation Instruction Based on RISC-V

“…Due to the extensibility of the RISC-V architecture, domain-specific accelerators have become easier to design and are ecologically compatible with RISC-V [16]. An AES coprocessor based on RISC-V is proposed in [17], which improves encryption efficiency and reduces resource overhead. In [18], a RISC-Vbased dedicated processor for the convolution operation is proposed, which is optimized using the Winograd algorithm to reduce the operation cycles.…”