A Compact, Low Jitter, CMOS 65 nm 4.8–6 GHz Phase-Locked Loop for Applications in HEP Experiments Front-End Electronics

Mazza, G.; Panati, Serena

doi:10.1109/tns.2018.2826141

“…Overall, the phase noise characteristic of the SQVCO is slightly better than for the PQVCO due to the tail-noise filter [40] in the form of the coupling inductor present in the SQVCO. Table 1 presents a performance comparison of the implemented QVCOs with respect to previously reported VCOs [28,29,46,47] and QVCOs [33] which are studied under radiation (TID) exposure. Similar to [28], the implemented QVCOs in this work are targeted to operate in the s-band.…”

Section: Resultsmentioning

confidence: 99%

Radiation Tolerant Electronics, Volume II

2023

0

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“…Overall, the phase noise characteristic of the SQVCO is slightly better than for the PQVCO due to the tail-noise filter [40] in the form of the coupling inductor present in the SQVCO. Table 1 presents a performance comparison of the implemented QVCOs with respect to previously reported VCOs [28,29,46,47] and QVCOs [33] which are studied under radiation (TID) exposure. Similar to [28], the implemented QVCOs in this work are targeted to operate in the s-band.…”

Section: Resultsmentioning

confidence: 99%

TID Sensitivity Assessment of Quadrature LC-Tank VCOs Implemented in 65-nm CMOS Technology

Karmakar

¹

,

Smedt

²

,

Leroux

³

2022

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This article presents a comprehensive assessment of the ionizing radiation induced effects on the performance of quadrature phase LC-tank based voltage-controlled-oscillators (VCOs). Two different quadrature VCOs (QVCOs) that are capable of generating frequencies in the range of 2.5 GHz to 2.9 GHz are implemented in a commercial 65 nm bulk CMOS technology to target for harsh radiation environments like space applications and high-energy physics (HEP) experiments. Each of the QVCOs consumes 13 mW power from a 1.2 V supply. The architectures are based on the popular implementation of two different types of QVCOs: parallel-coupled QVCO (PQVCO) and super-harmonic coupled QVCO (SQVCO). The various performance metrics (oscillation frequency, quadrature phase, phase noise, frequency tuning range, and power consumption) of the two different QVCOs are evaluated with respect to a Total ionizing Dose (TID) up to a level of approximately 100 Mrad (SiO2) through X-ray irradiation. During irradiation, the electrical characterization of the samples of the prototype are performed under biased condition at room temperature. Before irradiation, the QVCOs (PQVCO and SQVCO) achieve phase noise equal to −115 dBc/Hz and −119 dBc/Hz at 1 MHz offset, resulting in figure-of-merit (FoM) of −172.2 dBc/Hz and −176.4 dBc/Hz respectively. The test-setup of the TID experiment is discussed and the results obtained are statistically analyzed in this article to perform a comparative study of the performance of the two different QVCOs and evaluate the effectiveness of the radiation hardened by design techniques (RHBDs) employed in the implementations. Post-irradiation, the overall variations of the frequencies of the oscillators are less than 1% and the change in tuning range (TR) is less than 5% as observed from the tested samples.

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“…In Table 2 , a comparison with the state-of-the-art rad-hard PLLs is performed. In [ 15 ], a CP-PLL in 65 nm technology for high-energy physics is presented. It generates a tunable output frequency in the range of 4.8–6 GHz, which is slightly lower the SpaceFibre standard.…”

Section: Discussionmentioning

confidence: 99%

“…It generates a tunable output frequency in the range of 4.8–6 GHz, which is slightly lower the SpaceFibre standard. As reported in [ 15 ], the CP-PLL was not designed to be SEE tolerant; indeed, a simple PFD was used in the PLL loop. Instead, in this work, a TMR PFD was implemented to increase the hardness against SEE.…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL

Mestice

¹

,

Neri

²

,

Ciarpi

³

et al. 2020

Sensors

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The design of a Phase-Locked Loop (PLL) to generate the clock reference for the new Spacefibre standard is presented in this paper. Spacefibre has been recently released by the European Space Agency (ESA) and supports up to 6.25 Gbps for on-board satellite communications. Taking as a starting point a rad-hard 6.25 GHz Voltage Controlled Oscillator in 65 nm technology, this work presents the design of the key blocks for an integrated PLL: a Triple Modular Redundancy Phase/Frequency Detector, a Charge Pump, and a passive Loop Filter. The modeling activities carried out in an Advanced Design System have proven that the proposed PLL can be completely integrated on-chip, with a Loop Filter area consumption of only 6000 µm2 (considering the 65 nm technology). The design of active circuits has been carried out at the transistor level in a Cadence Virtuoso environment, implementing both system and layout rad-hard techniques, and different solutions are discussed in this paper. As a result, a compact (0.09 mm2), low power (10.24 mW), dead zone free and rad-hard PLL is obtained with a Phase Noise below −80 dBc/Hz @ 1 MHz. A preliminary block view and floor plan of the test chip is also proposed.

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A Compact, Low Jitter, CMOS 65 nm 4.8–6 GHz Phase-Locked Loop for Applications in HEP Experiments Front-End Electronics

Cited by 9 publications

References 14 publications

Radiation Tolerant Electronics, Volume II

Radiation Tolerant Electronics, Volume II

TID Sensitivity Assessment of Quadrature LC-Tank VCOs Implemented in 65-nm CMOS Technology

Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL

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