A Compact Model for Double-Gate Heterojunction Tunnel FETs

Dong, Yunpeng; Zhang, Lining; Li, Xiangbin; Lin, Xinnan; Chan, Mansun

doi:10.1109/ted.2016.2604001

Cited by 42 publications

(23 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2 can be expressed as

G_{total, s} = G_{1} + G_{2} + \dots + G_{n} - G_{1 D} - G_{2 D} - \dots - G_{false(n - 1 false) D} .

When the gate voltage is negative, the source to channel tunnelling process ends and the channel to drain tunnelling process occurs, resulting in the ambipolar effect. The total area

G_{total, d}

under the profile of

G_{btbt, d}

can be obtained by using a similar approach and the drain current of the strained JLNW TFET can be expressed as

I_{DS} = q π t_{si}^{2} f_{fermi} false(G_{total, s} + G_{total, d} false) / 4

where

f_{fermi} = 1 - 2 / false(1 + \exp false(q V_{DS} / η k T false) false)

guarantees a zero drain current at

V_{DS} = 0

and

η

is an empirical parameter [27].…”

Section: Drain Current Modelmentioning

confidence: 99%

Analytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on virtual substrate

Zhang

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

“…2 can be expressed as

G_{total, s} = G_{1} + G_{2} + \dots + G_{n} - G_{1 D} - G_{2 D} - \dots - G_{false(n - 1 false) D} .

When the gate voltage is negative, the source to channel tunnelling process ends and the channel to drain tunnelling process occurs, resulting in the ambipolar effect. The total area

G_{total, d}

under the profile of

G_{btbt, d}

can be obtained by using a similar approach and the drain current of the strained JLNW TFET can be expressed as

I_{DS} = q π t_{si}^{2} f_{fermi} false(G_{total, s} + G_{total, d} false) / 4

where

f_{fermi} = 1 - 2 / false(1 + \exp false(q V_{DS} / η k T false) false)

guarantees a zero drain current at

V_{DS} = 0

and

η

is an empirical parameter [27].…”

Section: Drain Current Modelmentioning

confidence: 99%

Analytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on virtual substrate

Zhang

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

“…Multiplication by the factor f ensures a zero line tunnelling current [16] at V DS = 0 V, and the factor (V GS − V onset ) 2.5 results in zero tunnelling current at V GS = V onset . It is assumed that the drain current below V onset is due to the SRH generation.…”

Section: Modelling Of Line Tunnelling Currentmentioning

confidence: 99%

“…Most of them are based on the solution of Poisson's equation in the device and estimation of the tunnelling current using Kane's/WKB approach. Although analytical modelling of point tunnelling homojunction and heterojunction devices has been discussed in several studies [12][13][14][15][16][17], the analytical model development of the line TFETs have received less attention [18,19]. A few models of the line TFETs [20,21] have been reported that are valid only for depletion-based line tunnelling current and not applicable for epitaxial layer-based line TFETs.…”

Section: Introductionmentioning

confidence: 99%

Analytical modelling and device design optimisation of epitaxial layer‐based III–V tunnel FET

Dubey¹,

Kaushik²,

Simoen

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

The line tunnelling and heterojunction are two important techniques to improve the performance of the tunnelling field-effect transistors (TFETs). The TFETs that utilise both of these techniques perform superior to the conventional TFETs. The recently proposed T-shaped TFET (TTFET) is one such heterojunction-based line tunnelling device that is expected to become energy efficient switch. For the first time, a physics-based analytical model for surface potential and drain current of epitaxial layer-based heterojunction line TFET has been developed. The model describes the impact of device design parameters on the electrical performance of the device. The Poisson equation is solved with precise boundary conditions to obtain the surface potential model. Kane's model is used to calculate drain current by utilising surface potential model. A good agreement between Synopsys technology computer-aided design simulation and analytical model is observed with 5.4% error in ON current at V GS = V DS = 0.5 V, an average error of 5.80% in surface potential and 7.24% in transconductance. Finally, a device design guideline is presented according to the analytical expressions.

show abstract

“…The source depletion effects can be considered through the depletion approximation as in Refs. [14], [15], where ( ) = ( , − Δ + ) exp(− / ) − . Δ, being the energy bending of source depletion region, is the changed channel potential energy at x = 0 to keep the source band-gap constant, and can be obtained by the continuity conditions at the source/channel junction [14], [15].…”

Section: B Analytical Model Based On Timmentioning

confidence: 99%

An Accurate Analytical Model for Tunnel FET Output Characteristics

Guan

Carrillo-Nuñez

et al. 2019

IEEE Electron Device Lett.

View full text Add to dashboard Cite

The analytical models for the output characteristics of tunnel FETs (TFETs) based on Maxwell-Boltzmann (MB) statistics have some accuracy issues, especially in linear region of operation, when compared with more sophisticated numerical approaches. In this letter, by exploiting the thermal injection method (TIM), an accurate analytical model for the TFET potential profile is proposed. Although the approach is initially envisaged for heterojunction TFETs (H-TFETs), it could be straightforwardly adopted for homojunction TFETs. After an accurate description of the potential profile is obtained, the current is then computed by means of a Landauer-like expression. Comparison with numerical simulations at different bias conditions shows that the predicted output characteristics qualitatively improve, leading to a significant enhancement in accuracy at a much less computational cost.

show abstract

A Compact Model for Double-Gate Heterojunction Tunnel FETs

Cited by 42 publications

References 33 publications

Analytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on virtual substrate

Analytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on virtual substrate

Analytical modelling and device design optimisation of epitaxial layer‐based III–V tunnel FET

An Accurate Analytical Model for Tunnel FET Output Characteristics

Contact Info

Product

Resources

About