A compact model for the well-depleted 1-T pixel sensor based on silicon-on-insulator technology

Abstract

Silicon-on-Insulator (SOI) based one transistor (1-T) pixel sensor is a promising candidate for high resolution image sensor and in-sensor computing. In this work, a compact model for the photoresponse of the well-depleted SOI 1-T pixel sensor is proposed from the perspective of physical process. The model successively explains the photoelectron accumulation, the photoelectron redistribution and the modulation on the transistor according to the electron drifting/diffusing mechanism, the capacitor-voltage (C-V) relationship and the current solution from BSIM-IMG. The model agrees well with the experimental results from the 1-T pixel sensor fabricated by the 22nm fully-depleted SOI (FDSOI) technology, as well as the simulation results from TCAD. The extraction scheme of model parameter is also provided to facilitate the model use.

Gate-controlled gain tuning of fully depleted silicon-on-insulator-based 1 T pixel for in-sensor white balance

“…The FDSOI-based 1 T pixel sensor 15,[25][26][27][28][29] has been extensively studied in the past few years, and is becoming an outstanding candidate due to its potential of higher resolution and excellent CMOS compatibility. In this work, the 1 T pixel 15,30,31) is composed of an n-type nMOSFET for signal readout and a p-well under the buried oxide (BOX) for sensing. According to the transistor transfer characteristics, the 1 T pixel output gain can be modulated by the MOSFET gate at different voltage levels.…”