Two type CMOS-compatible complementary phototransistors (CPTs) with NMOS or PMOS transistor are proposed in this work for in-sensor vector-matrix multiplication (VMM). The CPT is fabricated by the 22nm FDSOI process technology and composed of a MOSFET with a p-doped well under the buried oxide (BOX). The well serves for photoelectron generation and affects the on-state current of the MOSFET by the photoelectrons. The bidirectional and tunable photoresponsivity characteristics as well as the optical-electrical signed multiplication operation (average error <2.5%) are experimentally demonstrated in the pair of CPTs. The in-sensor VMM is verified by typical artificial neural networks using the CPT array as the imageinput layer. Simulated results show slight inference accuracy losses (<1%) in LeNet3 for MNIST and VGG11/VGG16 for CIFAR-10 recognition.

Silicon-on-Insulator (SOI) based one transistor (1-T) pixel sensor is a promising candidate for high resolution image sensor and in-sensor computing. In this work, a compact model for the photoresponse of the well-depleted SOI 1-T pixel sensor is proposed from the perspective of physical process. The model successively explains the photoelectron accumulation, the photoelectron redistribution and the modulation on the transistor according to the electron drifting/diffusing mechanism, the capacitor-voltage (C-V) relationship and the current solution from BSIM-IMG. The model agrees well with the experimental results from the 1-T pixel sensor fabricated by the 22nm fully-depleted SOI (FDSOI) technology, as well as the simulation results from TCAD. The extraction scheme of model parameter is also provided to facilitate the model use.

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