A compact rail-to-rail output stage for CMOS operational amplifiers

Sekerkiran, B.

doi:10.1109/4.736663

Cited by 18 publications

(3 citation statements)

References 4 publications

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“…The ESD-protecting circuit consists of MDI--MD9, will be used to control over current of the FES circuit through negative feedback [6]. MD9 has a small WIL ratio.…”

Section: Fes Circuitmentioning

confidence: 99%

IC for neural signal regeneration

Wang

2008

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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Based on the 4-channels neural signal regeneration system which was realized by using discrete devices and successfully used for in-vivo experiments of rats and rabbits, an integrated circuit (IC) with 6-channels of neural signal regeneration has been designed and realized in CSMC's 0.6Jlm CMOS technology. The IC consists of a neural signal amplifier with adjustable gain, a buffer stage, and a function electrical stimulation (FES) stage. The neural signal detecting circuit amplifies the detected weak signal come from the electrode to such a voltage that the FES circuit can be driven appropriately. The FES circuit amplifies the signal further so that the neural signal can be regenerated through the stimulating electrode. The neural signal regenerating IC occupies a die area of 2.82mm x 2.00mm. Under double supply voltages of ±2.5V, the DC power consumption is less than 50 mW. The on-wafer measurement results are as follows: the output resistor is 118 mn, the 3dB bandwidth is greater than 30 kHz, and the gain can be variable from 50dB to 90dB. The circuit has been used for in-vivo experiments on the rat's sciatic nerve as well as spinal cord with the cuff type electrode array or a needle twin-electrode, and the neural signal has been regenerated successfully both on a rat's sciatic nerve bundle and on a spinal cord.

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“…The ESD-protecting circuit consists of MDI--MD9, will be used to control over current of the FES circuit through negative feedback [6]. MD9 has a small WIL ratio.…”

Section: Fes Circuitmentioning

confidence: 99%

IC for neural signal regeneration

Wang

2008

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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“…3 consists of a class-AB output stage with error amplifiers whose output resistance is controllable. Although the quiescent current control is an important design constraint [10], [11], the line driver proposed in this paper lacks a quiescent current stabilizer circuit since the main motivation in this design is to apply impedance tuning to a class-AB buffer. The quiescent current is set by the gate-to-source voltages of M and M , which is further controlled by the error amplifiers in feedback.…”

Section: A Class-ab Output Stagementioning

confidence: 99%

A 3.3-V CMOS adaptive analog video line driver with low distortion performance

Ramachandran

Dinc

Karsilayan

2003

IEEE J. Solid-State Circuits

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An analog line driver for video applications is presented. Utilizing a class-AB error amplifier structure, the design achieved 1.2-V peak-to-peak output swing with better than 42-dB linearity for frequencies up to 5 MHz. An adaptive tuning scheme for output impedance matching using peak detection is used to provide uniform performance across line impedance variations. The circuit is designed in AMI 0.5-CMOS technology and has a tuning range of 70-180 with a power consumption of about 26.4 mW at 75load.

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“…Among these, a pseudo source follower seems to be the appropriate choice. Pseudo source follower consists of a pair of complementary common-source stages and a pair of complementary error amplifiers at the output (Brehmer and Wieser, 1983;Ahuja et al, 1984;Fisher, 1985;Nagaraj, 1989;Nosratinia et al, 1995;Saether et al, 1996;Sekerkiran, 1999). The follower offers small output impedance and, at the same time, can handle large output voltage swing.…”

Section: Introductionmentioning

confidence: 99%

A simple rail‐to‐rail CMOS voltage follower

Kasemsuwan

Nakhlo

2009

Microelectronics International

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Purpose -The paper aims to present a simple rail-to-rail CMOS voltage follower. Design/methodology/approach -The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 mm CMOS technology, and operates under the supply voltage of 1.5 V. HSPICE is used to verify the circuit performance. Findings -The simulations show output voltage swing of^0.6 V (300 V load) with the total harmonic distortion of 0.55 per cent at the operating frequency of 3 MHz. The bandwidth and power dissipation are 657 MHz and 405 m W, respectively. Originality/value -A simple rail-to-rail CMOS voltage follower is presented.

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A compact rail-to-rail output stage for CMOS operational amplifiers

Cited by 18 publications

References 4 publications

IC for neural signal regeneration

IC for neural signal regeneration

A 3.3-V CMOS adaptive analog video line driver with low distortion performance

A simple rail‐to‐rail CMOS voltage follower

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