A Comparative Study of Loop Filter Alternatives in Second-Order High-Pass $\Delta\Sigma$ Modulators

Khushk, Hasham Ahmed; Loumeau, Patrick; Nguyen, Van Tam

doi:10.1109/tcsi.2011.2157732

Cited by 6 publications

(1 citation statement)

References 17 publications

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“…However, due to the charge injection and clock feed-through at the chopper switches, residual offset is generated, which increases the total offset [20,21]. For the case with high frequency input, mirrored integrator is introduced to form a highpass SDM [22,23,24,25], which is inherently immune to the DC offset. The high-pass SDM will also generate the residual offset, which is similar to the SDM with chopper-stabilization.…”

Section: Introductionmentioning

confidence: 99%

A sigma-delta modulator with residual offset suppression

Wu¹,

Zhang²,

Chen³

et al. 2021

IEICE Electron. Express

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This Letter presents a low-residual-offset second-order sigma-delta modulator. By inserting a chopper working at low frequency to the mirrored integrator at the first stage of the modulator, the original residual offset is transferred to a high frequency, which can be removed by the filter. Besides, by applying the second-order fractal sequence as the timing of the new added chopper, the residual offset accumulation problem due to the integration at the second stage can be avoided. To evaluate the effect of residual offset suppression conveniently, a programmable timing is integrated to the design to control the state of the added chopper. The presented modulator is fabricated in a 0.18 um CMOS technology, the core area of which is 0.38 mm 2 . Based on the measurement results, the DC offset of the sigma-delta modulator with the proposed method is reduced by 85.6 μV. The modulator realizes 64.8 dB dynamic range with 1 MHz sampling rate, which consumes 0.96 mW from a 3.3 V supply.

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