A reconfigurable low-pass/high-pass $$\varDelta \varSigma$$ Δ Σ ADC suited for a zero-IF/low-IF receiver

A 96.4 dB high-pass delta-sigma modulator with dynamic biasing and tree-structured DEM

“…HP∆Σ ADCs were mainly investigated for CMOS RF direct-conversion and low-IF receivers due to their ability to process narrow-band signals located above the DC offset and flicker noise corner [1]. However, the impact of the clock jitter in those applications is substantially high and the folding of the image frequency, due to adjacent channels, is a challenging problem to solve.…”