A comparison of core power gating strategies implemented in modern hardware

AroraManish,; ManneSrilatha,; EckertYasuko,; PaulIndrani,; JayasenaNuwan,; TullsenDean,

doi:10.1145/2637364.2592017

Cited by 5 publications

(2 citation statements)

References 3 publications

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“…At the system level, energy-efficiency improvement techniques developed for the smart grid [Li et al 2015b], electric vehicles , and cloud computing [Li et al 2016] can be transformed to fit to the IoT energy efficiency problem, and protocols can be improved by reducing the number of transmissions and the amount of data in each transmission so as to cut down the power consumption for communication. At the circuit level, there are many promising low power techniques, such as power gating [Arora et al 2014], dynamic voltage and frequency scaling , and near-and subthreshold computing [Pinckney et al 2016;Li et al 2015]. At the device level, efforts have been spent on reducing leakage power consumption of transistors [Bardine et al 2014], and a great amount of power-harvesting devices are being designed and implemented to avoid the cost and scalability challenge of battery replacement in such large numbers [Klinefelter et al 2015;Battista et al 2014;Fadhil et al 2014].…”

Section: Problem Description 5 (Energy Efficiency) Given An Iot Systmentioning

confidence: 99%

Fundamental Challenges Toward Making the IoT a Reachable Reality

Xue

Nazarian

et al. 2017

ACM Trans. Des. Autom. Electron. Syst.

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Constantly advancing integration capability is paving the way for the construction of the extremely large scale continuum of the Internet where entities or things from vastly varied domains are uniquely addressable and interacting seamlessly to form a giant networked system of systems known as the Internet-of-Things (IoT). In contrast to this visionary networked system paradigm, prior research efforts on the IoT are still very fragmented and confined to disjoint explorations of different applications, architecture, security, services, protocol, and economical domains, thus preventing design exploration and optimization from a unified and global perspective. In this context, this survey article first proposes a mathematical modeling framework that is rich in expressivity to capture IoT characteristics from a global perspective. It also sets forward a set of fundamental challenges in sensing, decentralized computation, robustness, energy efficiency, and hardware security based on the proposed modeling framework. Possible solutions are discussed to shed light on future development of the IoT system paradigm. . 2017. Fundamental challenges toward making IoT a reachable reality: A model-centric investigation.

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Section: Problem Description 5 (Energy Efficiency) Given An Iot Systmentioning

confidence: 99%

Fundamental Challenges Toward Making the IoT a Reachable Reality

Xue

Nazarian

et al. 2017

ACM Trans. Des. Autom. Electron. Syst.

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“…When a power emergency strikes, a well-designed power management scheme should not only decrease the power consumption to meet the new power constraint but also reduce the impact on performance as much as possible. Prior work that investigated voltage/frequency scaling [3,4], shutting-down schemes [6,7,17], and specialization [8], can potentially be used to address, to varying degrees, the problem of power emergencies. For example, when power emergency occurs, we can scale down the voltage/frequency to cut down the power consumption.…”

Section: Introductionmentioning

confidence: 99%

TaPEr

Hui

Kandemir

Irwin

2015

Proceedings of the 12th ACM International Conference on Computing Frontiers

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A new challenge in multicore design is the management of dark silicon. Among the on-chip components, the cores and caches consume most of the power. We observe that parallel programs exhibit different scalability characteristics with respect to the number of cores and the size of caches. Running programs with fewer cores or smaller caches does not always degrade performance significantly. Based on these observations, we propose a scheme, called TaPEr, that can dynamically (1) predict the scalability of parallel programs with respect to core count and cache capacity; (2) re-allocate available power to cores or caches based on a program's scalability in order to satisfy the power constraints; and (3) achieve high performance (comparing with DVFS or simple shutdown schemes) at the same time.

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Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy

Asad

Öztürk

Jahed‐Motlagh

2017

Microprocessors and Microsystems

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Management of a problem recently known as "dark silicon" is a new challenge in multicore designs. Prior innovative studies have addressed the dark silicon problem in the fields of power-efficient core design. However, addressing dark silicon challenges in uncore component designs such as cache hierarchy, on-chip interconnect etc. that consume significant portion of the on-chip power consumption is largely unexplored. In this paper, for the first time, we propose an integrated approach which considers the impact of power consumption of core and uncore components simultaneously to improve multi/manycore performance in the dark silicon era. The proposed approach dynamically (1) predicts the changing program behavior on each core; (2) re-determines frequency/voltage, cache capacity and technology in each level of the cache hierarchy based on the program's scalability in order to satisfy the power and temperature constraints. In the proposed architecture, for future chip-multiprocessors (CMPs), we exploit emerging technologies such as non-volatile memories (NVMs) and 3D techniques to combat dark silicon. Also, for the first time, we propose a detailed power model which is useful for future dark silicon CMPs power modeling. Experimental results on SPEC 20 0 0/20 06 benchmarks show that the proposed method improves throughput by about 54.3% and energy-delay product by about 61% on average, respectively, in comparison with the conventional CMP architecture with homogenous cache system.

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A comparison of core power gating strategies implemented in modern hardware

Cited by 5 publications

References 3 publications

Fundamental Challenges Toward Making the IoT a Reachable Reality

Fundamental Challenges Toward Making the IoT a Reachable Reality

TaPEr

Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy

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