Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)
DOI: 10.1109/cicc.2002.1012895
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A comprehensive study of energy dissipation in lossy transmission lines driven by CMOS inverters

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Cited by 9 publications
(6 citation statements)
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“…However, energy dissipation due to interconnected primitives has limited improvements in operating frequency. Conventional CMOS does waste energy, and has been shown to be lossy [146], due to the heat dissipation at each logic transition. Adiabatic logic is a CMOS design paradigm where the current flow through the circuit is controlled such that the energy is recycled rather than dissipated since the input and output charges are kept separate [147].…”
Section: Charge Based Computing Debatementioning
confidence: 99%
“…However, energy dissipation due to interconnected primitives has limited improvements in operating frequency. Conventional CMOS does waste energy, and has been shown to be lossy [146], due to the heat dissipation at each logic transition. Adiabatic logic is a CMOS design paradigm where the current flow through the circuit is controlled such that the energy is recycled rather than dissipated since the input and output charges are kept separate [147].…”
Section: Charge Based Computing Debatementioning
confidence: 99%
“…In order to validate the analysis above, the numerical calculation was carried out as follows. For the given area A, the wire thickness t, the distance d, the resistivity ρ and the relative dielectric constant r , the stub length is decided for a given frequency f from eqn (5). The stub width w is decided by eqn (6).…”
Section: Numerical Analysismentioning
confidence: 99%
“…Stubs are widely used for impedance matching technique of wireline communications, where the loss of the transmission lines are ignored. Lossy transmission lines have been studied but only for signal wires [5].…”
Section: Introductionmentioning
confidence: 99%
“…The research described in [17] considers line inductance, however, the optimization criteria minimize delay using an unrealistic inductance model and do not consider power dissipation. The work described in [20]- [22] considers dynamic power dissipation while ignoring the short-circuit power of the load gate. The work described in [14], [15] considers power dissipation while ignoring the inductive behavior of the interconnect and, therefore, the effect of line inductance on the power characteristics.…”
Section: Introductionmentioning
confidence: 99%