A Computationally Efficient Compact Model for Ferroelectric FinFETs Switching with Asymmetric Non-Periodic Input Signals

Sahay, Shubham; Gaidhane, Amol D.; Chauhan, Yogesh Singh; Dangi, Raghvendra; Verma, Amit

doi:10.36227/techrxiv.18095684

“…For design exploration and performance evaluation of the timemode MAC accelerator utilizing Fe-FinFETs, an experimentally calibrated compact model for the ferroelectric FinFETs was used in HSPICE. This compact model for Fe-FinFETs is based on the self-consistent solution of the dynamics of the ferroelectric capacitor [25] connected to a baseline FinFET from the ASAP 7-nm technology PDK [26].…”

Section: Simulation Methodologymentioning

confidence: 99%

Ferroelectric FET Based Time-Mode Multiply-Accumulate Accelerator: Design and Analysis

kaur¹,

Rafiq²,

Gaidhane³

et al. 2022

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General-purpose multiply-accumulate (MAC) accelerators have become inevitable in the IoT edge devices for performing computationally intensive tasks such as deep learning, signal processing, combinatorial optimization, etc. The throughput and the energy-efficiency of the conventional digital processors and MAC accelerators are limited due to their sparse design owing to the von-Neumann architecture. Although mixed-signal time-mode MAC accelerators utilizing emerging non-volatile memories appear promising owing to their ability to perform in-memory MAC operation via the physical laws, their application is limited due to their incompatibility and complex integration with the CMOS-process, high sensitivity to process variations, large operating voltage/cell currents, etc. To mitigate these issues, in this work, we propose a time-mode MAC accelerator based on ferroelectric-FinFETs with CMOS-compatible doped-HfO2 in the gate stack. Our rigorous analysis reveals a trade-off between the performance metrics such as computational precision, area- and energy-efficiency of the proposed MAC accelerator. Therefore, we provide the necessary design guidelines to further optimize the performance. Extensive design space exploration and simulations exploiting an experimentally calibrated compact model for the doped HfO2 ferroelectric capacitor along with 7 nm-technology PDK from ARM (ASAP) indicates that the proposed MAC accelerator exhibits a record energy-efficiency of 2.612 PetaOperations/Joule , a considerably high area-efficiency of 88.5 bits/µm2 (including I/O peripheral circuitry) , and a throughput of 4.6 TeraOps/s while supporting a 4-bit MAC operation for a square weight matrix of size 200×200 which is sufficient for realistic inference tasks.

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“…In Eq. ( 4), w is calculated using P r , P s and V c to match the experimentally observed characteristics [35]. The local maxima and minima of the input voltage, termed as turning points, are calculated to mimic the effect of polarization history.…”

Section: A Our Spice Modeling and Validation Of Fefetmentioning

confidence: 99%

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

kumar¹,

Chatterjee²,

thomann³

et al. 2022

Preprint

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Today's data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET. We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a cross-layer manner is indispensable.

show abstract

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

kumar¹,

Chatterjee²,

thomann³

et al. 2022

Preprint

Self Cite

View full text Add to dashboard Cite

Today's data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET. We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a cross-layer manner is indispensable.

show abstract

A Computationally Efficient Compact Model for Ferroelectric FinFETs Switching with Asymmetric Non-Periodic Input Signals

Cited by 3 publications

References 14 publications

Ferroelectric FET Based Time-Mode Multiply-Accumulate Accelerator: Design and Analysis

Ferroelectric FET Based Time-Mode Multiply-Accumulate Accelerator: Design and Analysis

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

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