A constraint management system for IC physical design

Malavasi, E.; Charbon, Edoardo; Arsintescu, B.G.; Kao, W.H.

doi:10.1109/sbcci.1998.715450

Cited by 7 publications

(4 citation statements)

References 8 publications

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“…While the overall quality of constraints can be improved by adopting a good design methodology [3], or by using a constraint management system [9], it remains a laborious task to debug and fix constraint problems. Based on our communications with advanced designers in the industry, the state of the art process to debug and fix constraint problems remains an iterative manual trial-and-error process, with some help from in-house scripts or commercial tools that can check subsets of constraint issues [1] [2].…”

Section: Related Workmentioning

confidence: 99%

Constraint analysis and debugging for multi-million instance SoC designs

Long

Mize

Moon

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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Timing constraints are used by implementation tools in all design stages in modem design flows. With the growing complexity of designs and constraints, it is increasingly challenging to identify, diagnose, and fix constraint problems. In this paper, we present the technology of an interactive constraint debugger that automatically checks constraint problems, and provides context-sensitive diagnosis and fix suggestions. Our extensive user feedback shows that the tool significantly improves designer productivity.978-1-4244-6455-5/10/$26.00 ©2010 IEEE

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Section: Related Workmentioning

confidence: 99%

Constraint analysis and debugging for multi-million instance SoC designs

Long

Mize

Moon

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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“…This approach requires a comprehensive and consistent constraint data management system, which must be supported by each relevant design tool. Malavasi et al [10] introduced basic concepts and requirements for constraint management systems. Various proprietary constraint management systems are already available in existing IC design environments.…”

Section: Related Workmentioning

confidence: 99%

“…In a top-down analog system design flow, the process of translating high-level specifications and constraints into component level parameters is denoted as constraint transformation [5,10]. In [9] Malavasi et al introduced the transformation problem of constraints for top-down IC design.…”

Section: Related Workmentioning

confidence: 99%

“…Solving the problem of automatic and semi-automatic generation and transformation of design constraints is of utmost importance with regard to verification in top-down design [5,9,10]. Based on their individual focus, many IC verification tools merely concentrate on a small number of specific verification tasks that are applied to a large number of objects.…”

Section: Introductionmentioning

confidence: 99%

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On the verification of high-order constraint compliance in IC design

Freuer

Jerke

Gerlach

et al. 2008

Proceedings of the Conference on Design, Automation and Test in Europe

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The increasing quality requirements on safety-critical electronic components and the rapid technological progress necessitate the compliance with all specified functional and non-functional design constraints. This paper introduces a novel verification method based on an unified data representation of constraints to enable multi-tool verification tasks. A Constraint Engineering System is presented which provides flexible, extensible, and multi-tool definitions of complex constraints and high-order verification tasks. Existing verification and simulation tools are combined so that the achieved complexity level of the high-order verification by far exceeds the level of the single tools. The shown examples target practical applications in analog system design and demonstrate the flexibility and the potential of this new verification approach.

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