A continuous-time &amp;#x03A3;&amp;#x0394; modulator with a Gm-C input stage, 120-dB CMRR and &amp;#x2212;87 dB THD

Sarhangnejad, Navid; Wu, Rong; Chae, Youngcheol; Makinwa, Kofi A. A.

doi:10.1109/asscc.2011.6123556

Cited by 9 publications

(6 citation statements)

References 7 publications

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“…Here, the exact value of τ c was calculated by numerically solving Eq. (12). Both considered loop filters were third order filters designed using the sigma delta toolbox [17] but with different values for the maximum NTF gain, H ∞ : i.e.…”

Section: Sdm With Lpsc-dac and Compensationmentioning

confidence: 99%

“…For every value of τ , the corresponding loop filter parameters (H(s) and τ c ) were calculated by numerically solving Eq. (12). Here, all input resistors (R 0 , R 1 , R and R eq ) were chosen equal to minimize the size of C lp,in and C lp, f b .…”

Section: A Noisementioning

confidence: 99%

“…(15) shows that the proposed compensation technique consists of matching an RC time constant with a time constant implemented with both a switched capacitor and an ordinary resistor. Since PVT-variations [12], [23], [24] have a different impact on the switched capacitor than on the resistors, they will result in mismatch between these time constants. PVTvariations will also cause a mismatch between the equivalent resistance of the two input branches of the first integrator.…”

Section: Variabilitymentioning

confidence: 99%

“…Unfortunately, adding this filter to the loop puts constraints on the modulator's noise transfer function (NTF) such that the noise shaping is affected. Solutions for this problem have been proposed in [3] and [12]. In the former, an extra zero is added to the loop filter after the first OpAmp to cancel the pole introduced by the low-pass filter, leading to the system of Fig.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs

Vercaemer

Raman

Rombouts

2019

IEEE Trans. Circuits Syst. I

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In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slewing requirements on the OpAmps in the modulator's loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC's disadvantageous trade-off between the modulator's jitter, slewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM's loop filter, noise-and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable.

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Section: Sdm With Lpsc-dac and Compensationmentioning

confidence: 99%

Section: A Noisementioning

confidence: 99%