A coupled two-stage ring oscillator

Rezayee, A.; Martin, K.

doi:10.1109/mwscas.2001.986327

Cited by 39 publications

(24 citation statements)

References 4 publications

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“…The sub-feedback loop is established as a fast loop against the slow loop through a normal feedback loop. Other similar ring oscillator architectures can also be found in the literature, such as the coupled ring oscillator [8].…”

Section: Existing Multiloop Ring Oscillator Architecturesmentioning

confidence: 99%

“…2, it can be seen that the additional loop is formed by either splitting the input NMOS transistors or by introducing an additional PMOS input transistors, along with some other necessary frequency-tuning and bias current devices. In the designs reported in [1,2,8], the input NMOS transistors are split for multiple input entries and this is illustrated in Fig. 2(a).…”

Section: Design Of the Proposed Multiloop Ghz Ring Oscillatormentioning

confidence: 99%

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A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology

Liu

Siek

Goh

et al. 2008

Analog Integr Circ Sig Process

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A novel delay stage for ring oscillator utilizing multiloop technique is presented in this paper. Different conventional delay stages for the multiloop ring oscillators have been reviewed and analyzed in this work. By using push-pull inverter as the secondary input in its delay cell, the proposed oscillator demonstrates a frequency improvement of up to 17% when compared with conventional designs. The fabricated oscillator is measured to cover a frequency range of 6.24-7.04 GHz. Operating in 1.8-V power supply, the oscillator manifests itself a phase noise of -107.7 dBc/Hz@10 MHz offset from a center frequency of 6.25 GHz. The proposed oscillator consumes a current of 40-51 mA from the 1.8-V supply and occupies an area of 440 lm 9 430 lm.

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Section: Existing Multiloop Ring Oscillator Architecturesmentioning

confidence: 99%

Section: Design Of the Proposed Multiloop Ghz Ring Oscillatormentioning

confidence: 99%

A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology

Liu

Siek

Goh

et al. 2008

Analog Integr Circ Sig Process

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show abstract

“…And the Half-Alexander configuration is one of classical Bang-Bang PDs, which tracks a data signal and only needs half of clock frequency compared to full-rate PDs. The thesis [9] proposed a phase detector for half-rate bang-bang CDR circuit, as shown in Fig. 5.…”

Section: Proposed Topologymentioning

confidence: 99%

A novel digital phase interpolation control for clock and data recovery circuit

Liu

et al. 2015

IEICE Electron. Express

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In this express, we present a new architecture of digital phase interpolation (PI) controller with clock and data loops, which can greatly reduce the jitter of recovery clock by reducing the probability of the coarse phase jumping and interpolating among several fine phases. A demo design was implemented using 0.13 µm CMOS technology for verification, and the simulation results demonstrate that the recovered clock of the presented architecture has a peak to peak jitter no more than 29 ps under 2.5 Gbps received data, which shows no coarse phase dithering happening. The area of this proposed PI controller is only 0.1 mm 2 .

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“…Recently even lower N (=2), was reported [7], as a means of increasing f o . However [7] used coupled ring oscillators, and results in extra complexity, as well as also consumes higher power.…”

Section: Introductionmentioning

confidence: 97%

Investigation of a high frequency CMOS unsaturated ring oscillator

Leung

2012

Analog Integr Circ Sig Process

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Investigation of a high frequency unsaturated ring oscillator with cross coupled load is presented, and oscillation frequency compared with multi-path high frequency ring oscillators. Stability of oscillation is shown heuristically, via geometric argument on a phase plane, where the presence of negative impedance in the cross coupled pair of the delay cell is deemed important. Oscillation frequency formula is presented, and design insight given. In addition, a novel design methodology on lowering its phase noise is developed. Simulations on example circuit designs using 0.18 lm CMOS technology demonstrate the higher frequency obtained, oscillation stability, frequency formula and design insight, as well as phase noise methodology.

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A coupled two-stage ring oscillator

Cited by 39 publications

References 4 publications

A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology

A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology

A novel digital phase interpolation control for clock and data recovery circuit

Investigation of a high frequency CMOS unsaturated ring oscillator

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