A crosstalk-aware timing-driven router for FPGAs

Wilton, Steven J. E.

doi:10.1145/360276.360292

Cited by 23 publications

(9 citation statements)

References 20 publications

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“…The effects of crosstalk can be modeled by an increase or decrease in the wiring capacitance of the victim net, which has a significant effect on the delay of a net [4]. Coupling between a pair of interconnects can result in two different crosstalk effects: a glitch or a delayed transition, depending on the nature of the signal transitions in interconnects as shown in Figure 1(a) and 1(b), respectively [5,6].…”

Section: Nature Of Capacitive Crosstalkmentioning

confidence: 99%

“…However, if the damping is large enough to alter the state of the circuit, then the oscillations can be approximated as either a glitch or a delayed transition [5]. As far as FPGAs are concerned the effect of crosstalk noise among interconnects is more observable as a delay variation (i.e., significant effect on delay of the net) or spurious transition [4]. This paper proposes a novel FPGA crosstalk test architecture for detecting crosstalk effects such as positive and negative glitches, as well as the rise and fall time delays among the interconnects in FPGAs.…”

Section: Nature Of Capacitive Crosstalkmentioning

confidence: 99%

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A BIST Technique for Crosstalk Noise Detection in FPGAs

Al-Assadi

Kakarla

2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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As Integrated Circuits are migrated to more advanced technologies, it has become clear that crosstalk noise is an important phenomenon that must be taken into account. Also, crosstalk noise has emerged as a serious problem in recent years, because more and more devices and wires have been packed on electronic chips. Despite being more immune to crosstalk noise than their ASIC (Application Specific Integrated Circuit) counterparts, the dense interconnected structures of FPGAs (Field Programmable Gate Arrays) invite more vulnerabilities to crosstalk noise. Due to the lack of electrical detail concerning FPGA devices it is quite difficult to test the faults caused by crosstalk noise. This paper proposes a new approach for detecting effects such as glitches and delays in transition due to crosstalk noise in FPGAs. This approach is similar to the BIST (Built-in Self Test) technique in that it incorporates the test pattern generator to generate the test vectors and the analyzer to analyze the crosstalk faults without any extra overhead for testing.

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Section: Nature Of Capacitive Crosstalkmentioning

confidence: 99%

Section: Nature Of Capacitive Crosstalkmentioning

confidence: 99%

A BIST Technique for Crosstalk Noise Detection in FPGAs

Al-Assadi

Kakarla

2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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“…The modifications to the router in this work bears some similarity to a previously proposed crosstalk-aware router for FPGAs [13], in that signals are routed such that they have unused adjacent tracks (if they have high activity or are timing critical). However, the difference between this work and prior work is that here we proposed to leave adjacent conductors unused to reduce the effective capacitance of used routing conductors, thereby reducing power and improving speed.…”

Section: Tool Supportmentioning

confidence: 99%

Optimizing effective interconnect capacitance for FPGA power reduction

Huda

Anderson

Tamura

2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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We propose a technique to reduce the effective parasitic capacitance of interconnect routing conductors in a bid to simultaneously reduce power consumption and improve delay. The parasitic capacitance reduction is achieved by ensuring routing conductors adjacent to those used by timing critical or high activity nets are left floating -disconnected from either V DD or GND. In doing so, the effective coupling capacitance between the conductors is reduced, because the original coupling capacitance between the conductors is placed in series with other capacitances in the circuit (series combinations of capacitors correspond to lower effective capacitance). To ensure unused conductors can be allowed to float requires the use of tri-state routing buffers, and to that end, we also propose low-cost tri-state buffer circuitry. We also introduce CAD techniques to maximize the likelihood that unused routing conductors are made to be adjacent to those used by nets with high activity or low slack, improving both power and speed. Results show that interconnect dynamic power reductions of up to ∼15.5% are expected to be achieved with a critical path degradation of ∼1%, and a total area overhead of ∼2.1%.

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“…The initial work done on this architecture by Betz [1] was modelled in a 0.35µm design process. Subsequent to this, Wilton, Ahmed and Sheng [31][7] [9] remodelled the architecture for a 0.18µm process which was used in this research.…”

Section: -Basic Logic Element (Ble)mentioning

confidence: 99%

Nearest neighbour interconnect architecture in deep submicron FPGAs

Roopchansingh

Rose

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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As FPGAs become mainstream system implementation vehicles, the desire to make their speed performance greater is stronger. In this work we seek to increase the speed of FPGAs by exploring the use of high speed Nearest Neighbour (NN) interconnections. Several commercial FPGA architectures provide these fast connections between adjacent logic blocks because they decrease the best-case delay between circuit elements with the goal of increasing overall performance. This work explores the architecture of these NN interconnects to determine topologies, quantities and distances that are good for performance and area. We develop an augmented architecture generation tool and CAD flow that enumerates and targets various portions of the NN architecture space. We show that certain architectures can achieve a 7.7% performance improvement at the cost of a 6.8% increase in total FPGA area when fully populated. We also show that a 6.4% improvement can be achieved for a more modest cost of 3.8% increase in area.i

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A crosstalk-aware timing-driven router for FPGAs

Cited by 23 publications

References 20 publications

A BIST Technique for Crosstalk Noise Detection in FPGAs

A BIST Technique for Crosstalk Noise Detection in FPGAs

Optimizing effective interconnect capacitance for FPGA power reduction

Nearest neighbour interconnect architecture in deep submicron FPGAs

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