A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture

Mucci, Claudio; Campi, Fabio; Deledda, A.; Fazzi, A.; Ferri, Maura; Bocchi, Massimo

doi:10.1109/ipdps.2005.14

Cited by 9 publications

(5 citation statements)

References 20 publications

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“…Architecture customizability evolved with the advent of processor description languages [95]. An early reconfigurable processor to have a high-level processor description is XiRisc [60]. Stretch [65] used the architecture template from Tensilica [85] for limited design exploration capability.…”

Section: Architecture Customizabilitymentioning

confidence: 99%

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Chattopadhyay

2013

VLSI Design

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For a design to survive unforeseen physical effects like aging, temperature variation, and/or emergence of new application standards, adaptability needs to be supported. Adaptability, in its complete strength, is present in reconfigurable processors, which makes it an important IP in modern System-on-Chips (SoCs). Reconfigurable processors have risen to prominence as a dominant computing platform across embedded, general-purpose, and high-performance application domains during the last decade. Significant advances have been made in many areas such as, identifying the advantages of reconfigurable platforms, their modeling, implementation flow and finally towards early commercial acceptance. This paper reviews these progresses from various perspectives with particular emphasis on fundamental challenges and their solutions. Empowered with the analysis of past, the future research roadmap is proposed.

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Section: Architecture Customizabilitymentioning

confidence: 99%

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Chattopadhyay

2013

VLSI Design

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“…This tool is used to evaluate the impact of several instruction set extensions and different operator combinations [28]. A similar approach is commonly used to define possible extensions for the standard instruction sets of industrial ASIPs [20]. Image processing algorithms present regular patterns like sequential image scans.…”

Section: Estimation Of Computing Resourcesmentioning

confidence: 99%

The eISP low-power and tiny silicon footprint programmable video architecture

Thevennin

Paindavoine

Letellier

et al. 2010

J Real-Time Image Proc

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International audienceCMOS sensors are now more and more frequently integrated into popular consumer products. Images from these sensors thus need to be digitally processed for display purposes. To do so, CMOS sensors are associated with dedicated components that keep power consumption low. However, use of dedicated components limits hardware flexibility and prevents updating of image processing algorithms. This paper describes the eISP, a programmable processing architecture that combines enough computational efficiency for 1080p HD video with silicon area and power characteristics suitable for the next generation of mobile phones (lower than 1 mm2 and 500 mW in TSMC 65 nm)

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“…The scope of prefabrication design space exploration is lacking in this approach. Mucci et al [2005] offered an interesting framework to do a generic design space exploration for the complete rASIP. The base processor is modeled using an ADL.…”

Section: Related Workmentioning

confidence: 99%

“…Conceptually, the reconfigurable unit can append the basic processor instruction set with further instructions and/or can run the existing instructions faster. Because of its immense potential, several rASIPs have been designed in the recent past [Mucci et al 2005;Mei et al 2004;Panainte et al 2004]. Interestingly, the idea of rASIP was available for years [Iseli and Sanchez 1995;Razdan and Smith 1994;Athanas and Silverman 1993].…”

Section: Introductionmentioning

confidence: 99%

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors

Chattopadhyay

Ishebabi

Chen

et al. 2008

ACM Trans. Embed. Comput. Syst.

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Modern application-specific instruction-set processors (ASIPs) face the daunting task of delivering high performance for a wide range of applications. For enhancing the performance, architectural features, for example, pipelining, VLIW, are often employed in ASIPs, leading to high design complexity. Integrated ASIP design environments, like template-based approaches and language-driven approaches, provide an answer to this growing design complexity. At the same time, increasing hardware design costs have motivated the processor designers to introduce high flexibility in the processor. Flexibility, in its most effective form, can be introduced to the ASIP by coupling a reconfigurable unit to the base processor. Because of its obvious benefits, several reconfigurable ASIPs (rASIPs) have been designed for years. This design paradigm gained momentum with the advent of coarse-grained FPGAs, where the lack of domain-specific performance common in general-purpose FPGAs are largely overcome by choosing application-dependent basic functional units. These rASIP designs lack a generic flow from high-level specification, resulting in intuitive design decisions and hard-to-retarget processor design tools. Although partial, template-based approaches for rASIP design is existent, a clear design methodology especially for the prefabrication architecture exploration is not present. In order to address this issue, a high-level specification and design methodology for partially reconfigurable VLIW processors is proposed in this article. To show the benefit of this approach, a commercial VLIW processor is used as the base architecture and two domains of applications are studied for potential performance gain.

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A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture

Cited by 9 publications

References 20 publications

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Ingredients of Adaptability: A Survey of Reconfigurable Processors

The eISP low-power and tiny silicon footprint programmable video architecture

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors

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