A $\Delta\Sigma$ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications

Xiang, Yu; Sun, Yun; Rhee, Woogeun; Ahn, Hyung Ki; Park, Byeong-Ha; Wang, Zhihua

doi:10.1109/jssc.2009.2022301

Cited by 27 publications

(9 citation statements)

References 11 publications

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“…The notches in each output spectrum correspond to the zeros of the FIR transfer function in each mode, showing that the embedded FIR filter suppresses the quantization noise as predicted by the transfer function. The results also imply that a customized noise shaping can be achieved with the propose method [23].…”

Section: Fir-embedded ∆σ Modulationmentioning

confidence: 66%

“…The semi-digital approach based on a finite-impulse response (FIR) filtering method offers moderate quantization noise reduction without using the DAC [22][23][24][25][26][27]. With wide bandwidth, out-of-band noise could be more problematic than in-band noise to meet the phase noise mask required by wireless standards.…”

Section: Fir-embedded ∆σ Modulationmentioning

confidence: 99%

“…Since noise reduction is done by the semidigital filtering method, the quantization noise suppression is more predictable with less dependency on PVT variations. In addition, the power and area of the FIR filtering circuitry can be scaled with the advanced CMOS technology when the phase-interpolated multimodulus divider is employed [23,26,27], while difficult for the DAC cancellation method.…”

Section: Fir-embedded ∆σ Modulationmentioning

confidence: 99%

“…18. Measured PLL output spectra with different FIR modes [23]. with the 3rd pole and 4th pole at 560 kHz and 1.77 MHz, respectively.…”

Section: Fir-embedded ∆σ Modulationmentioning

confidence: 99%

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Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded Design

Rhee¹,

Xu²,

Zhou³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ∆Σ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ∆Σ fractional-N PLLs are discussed with simulation and hardware results. High-order ∆Σ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.

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Section: Fir-embedded ∆σ Modulationmentioning

confidence: 66%

Section: Fir-embedded ∆σ Modulationmentioning

confidence: 99%

Section: Fir-embedded ∆σ Modulationmentioning

confidence: 99%

“…18. Measured PLL output spectra with different FIR modes [23]. with the 3rd pole and 4th pole at 560 kHz and 1.77 MHz, respectively.…”

Section: Fir-embedded ∆σ Modulationmentioning

confidence: 99%

See 2 more Smart Citations

Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded Design

Rhee¹,

Xu²,

Zhou³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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“…To relieve the trade-off limitation, FIR filtering technique has been an actively researched topic since it simply performs running averaging of DSM noise without affecting PLL loop dynamics. For the summing operation in FIR filtering, analog implementations such as phase blending [1] and the use of multiple CPs, PFDs, and dividers [2,5,6] suffer from power overhead and matching requirements as the number of taps increases. Recently, an eight-tap digitaldomain FIR filtering scheme was implemented in an alldigital PLL [7].…”

Section: Introductionmentioning

confidence: 99%

An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

Lee¹,

Jee²,

Kim³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a 1.9-GHz digital ΔΣ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in 0.11-μm CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

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Fractional‐N PLL

2023

Phase‐Locked Loops

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A $\Delta\Sigma$ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications

Cited by 27 publications

References 11 publications

Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded Design

Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded Design

An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

Fractional‐N PLL

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