A Delta–Sigma Modulator for Low-Power Analog Front Ends in Biomedical Instrumentation

Yoon, Younghyun; Duan, Quanzhen; Yeo, Jaejin; Roh, Jeongjin; Kim, Jong-Jin; Kim, Dong-Wook

doi:10.1109/tim.2016.2534358

Cited by 18 publications

(12 citation statements)

References 23 publications

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“…Low power, medium speed, and high resolution Delta-Sigma modulators (DSMs) are indispensable for effective detection of the cardiac signals with frequency band ranging from 0.01 to 300Hz or neural signals with frequency band ranging from sub-1Hz to 100Hz. Recently many DSMs have been reported for implantable biomedical devices in [13,14,15,16,17,18,19,20,21]. Most of the ULV DSMs are implemented by discrete-time (DT) topology.…”

Section: Introductionmentioning

confidence: 99%

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

Chen

Guo

2020

IEICE Electron. Express

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This paper presents an ultra-low-voltage (ULV) high-resolution low-power continuous-time delta-sigma modulator for implantable biomedical devices. The 2 nd -order single-bit modulator adopts feed-forward architecture and a new fully differential ULV amplifier to achieve high signalto-noise plus distortion ratio (SNDR) and power-efficient operation under 0.4-V supply. The amplifier employs a gate-body-input class-AB output topology with a local common-mode-feedback (CMFB) loop to achieve large output swing for less harmonic distortion with low power consumption. A robust clock generator is adopted to ensure modulator's consistent performances across ±10% power supply variation. The modulator is fabricated in a 130-nm CMOS technology with regular V T transistors. The measurement results show that the modulator achieves 75.5-dB SNDR and consumes 6.6-µW under nominal 0.4-V supply within a 500-Hz bandwidth. The achieved SNDR is the best one among the recent reported DSMs operating at 0.4V or below for implantable biomedical applications. The modulator also achieves a 69dB SNDR with 3.7-µW power consumption even operating at 0.32V supply.

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Section: Introductionmentioning

confidence: 99%

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

Chen

Guo

2020

IEICE Electron. Express

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“…The sigma‐delta analog‐to‐digital converter (SD‐ADC) is the main candidate for high‐resolution applications due to their noise shaping mechanism and inherent immunity to the circuit nonidealities and has been widely used in many applications, such as communication systems, audio signal processing, and biomedical imaging systems . For the wideband applications, such as the popular medical ultrasound imaging (1‐15 MHz), the multistage noise shaping (MASH) structure is ideally suitable due to its potential for achieving higher resolution performance, wideband operation, and system stability .…”

Section: Introductionmentioning

confidence: 99%

“…For the wideband applications, such as the popular medical ultrasound imaging (1‐15 MHz), the multistage noise shaping (MASH) structure is ideally suitable due to its potential for achieving higher resolution performance, wideband operation, and system stability . The linearity and SNDR of the modulator are expected to be as high as possible so that the imaging system could capture the analog biomedical input signal in its most original form and enhance the performance of imaging …”

Section: Introductionmentioning

confidence: 99%

“…The sigma-delta analog-to-digital converter (SD-ADC) is the main candidate for high-resolution applications due to their noise shaping mechanism and inherent immunity to the circuit nonidealities [1][2][3] and has been widely used in many applications, such as communication systems, [4][5][6] audio signal processing, [7][8][9] and biomedical imaging systems. [10][11][12] For the wideband applications, such as the popular medical ultrasound imaging (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15), the multistage noise shaping (MASH) structure is ideally suitable due to its potential for achieving higher resolution performance, wideband operation, and system stability. 13 The linearity and SNDR of the modulator are expected to be as high as possible so that the imaging system could capture the analog biomedical input signal in its most original form and enhance the performance of imaging.…”

Section: Introductionmentioning

confidence: 99%

“…13 The linearity and SNDR of the modulator are expected to be as high as possible so that the imaging system could capture the analog biomedical input signal in its most original form and enhance the performance of imaging. 11,12 Principle of the MASH sigma-delta modulator (SDM) is based on the use of multiple low-order SDM stages in a cascaded configuration. The gain coefficients of the integrators are used in the modulator to not only realize the effective signal transfer function (STF) and noise transfer function (NTF) but also control the input/output swings of the integrators in a reasonable range.…”

Section: Introductionmentioning

confidence: 99%

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A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

Fei

Zhang

et al. 2019

Circuit Theory & Apps

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Summary A high SNDR discrete‐time (DT) 2‐1 MASH sigma‐delta modulator (SDM) for 15‐MHz bandwidth was presented. Cascade of integrators with feedforward (CIFF) scheme, combined with the optimized gain coefficients, was adopted to avoid of the integrators. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. Five‐bit flash quantizer was adopted in both stages to improve the overall signal‐to‐noise and distortion ratio (SNDR) performance, and third‐order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated in a mature 0.18‐μm CMOS technology, the occupied area of the modulator was 0.24 mm2 and dissipation power 25.4 mW from a 1.8‐V voltage supply. As a sampling rate of 240 MHz for the input sampling and DAC and 480 MHz for the flash ADC, a SNDR of 90.2 dB over 15‐MHz signal bandwidth and the corresponding effective number of bits (ENOB) of 14.69 bit were achieved. The spurious‐free dynamic range (SFDR) was 98 dB with DEM turned on for a 3.75 MHz at −2.5‐dBFS input signal, and the figure of merit (FOM) was 30.7 fJ/conv. for 15‐MHz bandwidth. A 15‐MHz bandwidth multibit MASH2‐1 discrete‐time sigma‐delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. High‐order DEM was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18‐μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15‐MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high‐frequency biomedical imaging or sensing systems, and so on.

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A 10.7‐μ$$ \upmu $$A 103‐dB DR Hybrid Delta‐Sigma Modulator for Sensing Applications

Zhang,

Wu,

Tang

et al. 2024

Circuit Theory & Apps

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This paper reports a low‐power, high dynamic range second‐order delta‐sigma modulator (DSM) for sensing applications. The DSM employs a hybrid CIFF‐B topology, consisting of a continuous‐time first stage and a discrete‐time second stage. The first stage is an OTA‐based RC integrator with inherent anti‐aliasing properties, while the second stage is a switched‐capacitor integrator. Offset and noise in the first stage are mitigated by the chopper‐stabilization technique, while those in the second stage are suppressed through the gain provided by the first stage. Furthermore, the OTA‐sharing technology is utilized in the second stage to realize signal addition before quantization, reducing design complexity. The hybrid DSM prototype is fabricated with a 180‐nm CMOS process and occupies an area of 0.123 mm2. Measurement results show peak SNDR/SNR/SFDR values of 95.8, 97.1, and 102.8 dB, respectively, with a current consumption of 10.7 A from a 1.8‐V single supply. The reported DSM achieves a 103‐dB dynamic range in a 100‐Hz signal bandwidth, corresponding to a Schreier figure‐of‐merit (FoMs) value of 170.2 dB.

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A Delta–Sigma Modulator for Low-Power Analog Front Ends in Biomedical Instrumentation

Cited by 18 publications

References 23 publications

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

A 10.7‐μ$$ \upmu $$A 103‐dB DR Hybrid Delta‐Sigma Modulator for Sensing Applications

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A Delta–Sigma Modulator for Low-Power Analog Front Ends in Biomedical Instrumentation

Cited by 18 publications

References 23 publications

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

A 15‐MHz bandwidth double sampling MASH25b‐15b sigma‐delta modulator with DEM for multibit DACs

A 10.7‐μ$$ \upmu $$A 103‐dB DR Hybrid Delta‐Sigma Modulator for Sensing Applications

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A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs