A design assembly framework for FPGA back-end acceleration

Frangieh, T.; Athanas, Peter

doi:10.1109/reconfig.2012.6416718

Cited by 13 publications

(7 citation statements)

References 8 publications

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“…TFlow was compared with that of the standard Xilinx ISE design flow and QFlow [4], a hard macro-based backend acceleration flow. TFlow takes significantly less time in each of the stages of assembly.…”

Section: Resultsmentioning

confidence: 99%

Rapid modular assembly of Xilinx FPGA designs

Love

Athanas

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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Section: Resultsmentioning

confidence: 99%

Rapid modular assembly of Xilinx FPGA designs

Love

Athanas

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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“…qFlow, an incremental compilation technique developed at Virginia Tech [3], also uses hard macros to realize compilation speedups. Built on the TORC toolset [11], this flow is similar to HMFlow in a number of ways.…”

Section: Qflowmentioning

confidence: 99%

“…However, while the system logic may be unchanged from a previous compilation run, standard FPGA compilation flows typically do not preserve information from previous tool runs. Other studies have shown that using previously compiled components can improve design productivity [1] [2] [3].…”

Section: Introductionmentioning

confidence: 99%

Rapid FPGA design prototyping through preservation of system logic: A case study

Haroldsen

Nelson

White

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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FPGA designs often contain significant amounts of logic such as a board support package that remains unaltered throughout the design process. However, during normal operation, standard FPGA implementation tools re-implement the entire system, including the unchanged logic, adding to the turn around time of design iterations. Recently, FPGA implementation flows have appeared that allow preserving parts of a previously implemented design. In this study, we evaluate the potential speedups in implementation time achievable through preserving the unchanging portion of a design's implementation. We perform these evaluations using Xilinx Partitions, Xilinx SmartGuide, and the HMFlow rapid implementation tool.

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“…Design productivity is improved with a high-level graphical front-end (i.e. Azido) and an accelerated compilation process employing incremental implementation strategies facilitated by qFlow [13] and Xilinx Hierarchical Design Flow [14]. Futhermore, this framework supports the growth of the third-party "personalities ecosystem" through the distribution of open-source accelerator implementations.…”

Section: Bflow Contributionsmentioning

confidence: 99%

“…Acceleration of the bitstream compilation process is achieved by two methods, Xilinx Hierarchical Design Partitions flow [14] and qFlow [13], both incremental, partial implementation frameworks that reduce build times through high-level management of the Xilinx ISE implementation process. Both methods exploit the Convey AE architecture, which contains static, unchanging interface logic that consumes roughly 25% of each AE, and is reimplemented on every run of Convey's standard compilation flow.…”

Section: Partial Implementation Flows With Qflow and Partitionsmentioning

confidence: 99%

FPGA-based HPC application design for non-experts

Uliana

Kȩpa

Athanas

2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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In the current era of big-data computing, most non-engineer domain experts lack the skills needed to design FPGA-based hardware accelerators to address big-data problems. This work presents bFlow, a development environment that facilitates the assembly of such accelerators, specifically those targeting FPGA-based hybrid computing platforms, such as the Convey HC series. This framework attempts to address the above problem by making use of an abstracted, graphical front-end more friendly to users without computer engineering backgrounds than traditional tools, as well as by accelerating bitstream compilation by means of incremental implementation techniques. bFlow's performance, usability, and application to big-data life-science problems was tested by participants of an NSF-funded Summer Institute organized by the Virginia Bioinformatics Institute (VBI). In about one week, a group of four non-engineering participants made significant modifications to a reference Smith-Waterman implementation, adding functionality and scaling theoretical throughput by a factor of 32.

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A design assembly framework for FPGA back-end acceleration

Cited by 13 publications

References 8 publications

Rapid modular assembly of Xilinx FPGA designs

Rapid modular assembly of Xilinx FPGA designs

Rapid FPGA design prototyping through preservation of system logic: A case study

FPGA-based HPC application design for non-experts

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