A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation

Abstract

Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint. The algorithm executes on a hypergraph which represents the netlist. In this paper we propose a design-driven iterative partitioning algorithm for Verilog based on module instances instead of gates. We do this in order to take advantage of the design hierarchy information contained in the modules and their instances. A Verilog instance represents one vertex in the circuit hypergraph. The vertex can be flattened into multiple vertices in the event that a load balance is not achieved by instance based partitioning. In this case the algorithm flattens the largest instance and moves gates between the partitions in order to improve the load balance.Our experiments show that this partitioning algorithm produces a smaller cutsize than is produced by hmetis on a gate-level netlist. It produces better speedup for the simulation because it takes advantage of the design hierarchy.

Optimization of Parallel Discrete Event Simulator for Multi-core Systems

“…Researchers have explored reducing the impact of message latency in a number of ways [7], [28], [31], [20]. Model partitioning [18] and dynamic object migration [25] attempt to localize important dependencies, reducing the frequency of remote communication. Throttling attempts to avoid excessive rollbacks by limiting the simulation from speculating aggressively [29].…”

“…Efficient partitioning is necessary to reduce remote communication [30], [18]. However, most efforts in implementing parallel applications discover that application insights and awareness of the architecture are necessary to optimize the parallel implementation [26], [6], [11].…”

“…Previous works have demonstrated the importance of partitioning to reduce the communication frequency in PDES (e.g., [18]). Similarly, dynamic partitioning and workload rebalancing mechanisms have been proposed to repartition the simulation to recover dynamic behavior changes of the simulation model for both conservative (e.g., [4]) and optimistic (e.g., [25]) synchronization protocols.…”

Performance Evaluation of PDES on Multi-core Clusters

“…Several researchers have investigated approaches for reducing the number of messages [9], [5], or improving the communication performance [10], [11]. The communication frequency can be reduced with effective partitioning that maps the most commonly communicating objects to the same process [12], [13]. However, existing approaches have not studied partitioning in a system with heterogeneous latencies.…”

Partitioning on Dynamic Behavior for Parallel Discrete Event Simulation

“…For partitioning purposes, the simulation model is represented as a graph, where every vertex is a simulation object and every edge represents the fact that the two objects communicate during the simulation. A graph partitioning tool is then used to partition the graph to minimize the cut size (to reduce communication) while maintaining balanced partition sizes (to maintain load balancing) [1], [2].…”