A design for high-speed low-power CMOS fully parallel content-addressable memory macros

Miyatake, H.; Tanaka, Masanori; Mori, Yumi

doi:10.1109/4.924858

Cited by 111 publications

(42 citation statements)

References 16 publications

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“…The reduction of power consumption is linearly proportional to the reduction of the voltage [11][12]. The main challenge addressed by low-swing implementations is using a low-swing voltage without resorting to an externally generated reference voltage [18].…”

Section: Previously Techniquementioning

confidence: 99%

Low-Power Ternary Content-Addressable Memory Using Power Reduction of Match-Line and Search-Line

Kim¹,

Kim²

2018

IJIES

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Abstract:The challenge to solve in large capacity ternary content addressable memory (TCAM) is the large power consumption of search-line and match-line. In this paper, we propose a circuit that uses match-line selectivecharging scheme and low-swing search-line scheme simultaneously to reduce power consumption of search-line and match-line which occupies a large ratio in power consumption of TCAM. The circuit was verified by Hspice simulation using a 1.8V supply voltage in a CMOS 0.18 um CMOS process. The proposed 128x128 bit TCAM shows 45.4% power savings in match-line and 74.7% power savings in search-line compared to the conventional precharge high scheme in search cycle. Also, the minimum search cycle time is 3 ns (333MHz).

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Section: Previously Techniquementioning

confidence: 99%

Low-Power Ternary Content-Addressable Memory Using Power Reduction of Match-Line and Search-Line

Kim¹,

Kim²

2018

IJIES

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“…Nowadays, more hardware architects than ever look into CAM for high performance table lookup tasks [4] [5] [6]. A specifically interesting type of CAM, called Ternary CAM (TCAM) can store don't-care values in addition to 0's and 1's.…”

Section: A Prior Workmentioning

confidence: 99%

A Reconfigurable CAM Architecture for Network Search Engines

Nourani

Vijayasarathi

Balsara

2006

2006 International Conference on Computer Design

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“…In the past decade, much research on energy reduction has focused on the circuit and technology domains ( (Pagiamtzis and Sheikholeslami, 2006) provides a comprehensive survey on CAM designs from circuit to architectural levels). Several works on reducing CAM power consumption have focused on reducing matchline power (Miyatake et al, 2001;Arsovski et al, 2003). The reduction in number of comparisons may help to improve system performance and conserve system resources such as network bandwidth, memory capacity and disk space.…”

Section: Introductionmentioning

confidence: 99%

Comparative Power Analysis of Precomputation Based Content Addressable Memory

Arun¹

2011

Journal of Computer Science

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Problem statement: In this study we discus about Signature Detection Technique (SDT) used in Network Intrusion Detection System (NIDS). Design of SDT using Content Addressable Memory (CAM) is discussed. Approach: Two novel architectures, XOR and ones count based Pre computation CAM architectures are proposed and implemented in third party back end tool with 0.18 mm technology, power consumptions are compared. Results: Proposed architecture consumes 90% less power added with 5.2% increment in speed. Conclusion: Power reduction was achieved by reducing the number of bit comparisons of pre computation technique.

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A design for high-speed low-power CMOS fully parallel content-addressable memory macros

Cited by 111 publications

References 16 publications

Low-Power Ternary Content-Addressable Memory Using Power Reduction of Match-Line and Search-Line

Low-Power Ternary Content-Addressable Memory Using Power Reduction of Match-Line and Search-Line

A Reconfigurable CAM Architecture for Network Search Engines

Comparative Power Analysis of Precomputation Based Content Addressable Memory

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