A design-for-reliability approach based on grading library cells for aging effects

Arasu, Senthil; Nourani, Mehrdad; Carulli, John M.; Butler, K.M.; Reddy, V.

doi:10.1109/test.2013.6651923

Cited by 9 publications

(2 citation statements)

References 14 publications

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“…However, if there are a large number of critical paths, as is typical in circuits, then implementing a large set of critical paths entails a high overhead. Moreover, the ring oscillators or the replica critical paths do not share the same ambient environment because of the difference in their on-die location and the critical paths within a datapath can change as a result of degradation [18]. Hence, this approach may not produce an accurate prediction of the aging rate of the true critical paths.…”

Section: Introductionmentioning

confidence: 99%

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements

Cha¹,

Chen²,

Liu³

et al. 2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

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Negative Bias Temperature Instability (NBTI) is a serious reliability issue for pMOS transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a new method to determine the NBTI model parameters through I/O circuit measurements. We determine a relationship between and signature signal degradation and fit a model to the simulation results. The signature signal involves the calculation of the degradation in the voltage signature, measured as delay and amplitude shifts. Given an estimate of , we find NBTI model parameters. Then, using the NBTI parameters at test conditions, we scale to use conditions and calculate lifetime. The methodology enables the extraction of NBTI model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to identify chips that are more vulnerable to NBTI.

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Section: Introductionmentioning

confidence: 99%

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements

Cha¹,

Chen²,

Liu³

et al. 2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

show abstract

“…Alternatively, ring oscillators [14] or replica critical paths [15], [16] are used to analyze degradation. However, the ring oscillators or the replica critical paths do not share the same ambient environment because of the difference in their on-die location and the critical paths within a datapath can change as a result of degradation [17]. Hence, this approach may not produce an accurate prediction of the aging rate of the true critical paths.…”

Section: Introductionmentioning

confidence: 99%

System-level estimation of threshold voltage degradation due to NBTI with I/O measurements

Cha

Chen

Milor

2014

2014 IEEE International Reliability Physics Symposium

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With the scaling of CMOS technology, Negative Bias Temperature Instability (NBTI) and Process Variations (PV) are serious issues for transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a method to determine the initial average channel length (L) and threshold voltage () for individual chips, together with NBTI model parameters through I/O measurements. We determine a relationship between , , and ground signal variation and fit models to the simulation results. The voltage of the ground signal is used for the calculation of the delay and amplitude shifts which are used to extract PV and NBTI parameters. Then, we calculate the lifetime for each chip individually using calibrated NBTI models, accounting for process variations. The methodology enables the extraction of NBTI and PV model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to differentiate chips that have different parameters initially and are more or less vulnerable to NBTI.

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An all-digital adaptive approach to combat aging effects in clock networks

Arasu

Nourani

Luo

2015

2015 6th Asia Symposium on Quality Electronic Design (ASQED)

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A design-for-reliability approach based on grading library cells for aging effects

Cited by 9 publications

References 14 publications

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements

System-level estimation of threshold voltage degradation due to NBTI with I/O measurements

An all-digital adaptive approach to combat aging effects in clock networks

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