A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

Abstract

SUMMARYThis paper presents a methodology to design reconfigurable switched-capacitor (SC) delta-sigma modulators Ms) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for lowbandwidth, medium-to-high resolution specifications, which are common in bio-medical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class-A and class-AB OTAs is presented. The power-optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution or program all sampling capacitors to the required resolution. The second approach results in the best trade-off between power efficiency and simplicity. A reconfigurable ΔΣM for bio-medical applications is designed at transistor-level in a 0.18μm CMOS process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%; validating thus the proposed approach.

Design‐oriented model for power‐driven design optimization of SC‐ΣΔ modulators

“…Using the model in Schreier, 28 several modulator topologies can be investigated. A very low power consumption may be achieved by resorting to a multibit modulator, 3 but the effect of the nonlinearity of the D/A converter in the signal path must be carefully evaluated and removed by means of suitable techniques. Therefore, a more robust solution based on third-order cascade-of-integrators with feed-forward topology with a single-bit quantizer was preferred for its lowest sensitivity to capacitance mismatch and the small C f ∕C s ratio.…”

“…2 Sensor interfaces to be implemented in wireless sensor nodes and in biomedical applications often require a small signal bandwidth (ie, hundreds of Hz) together with a medium-to-high resolution. 3 The key block of this oversampling converter is the ΣΔ modulator to be implemented with continuous time (CT) or switched-capacitor (SC) integrators, and with a single-bit or a multibit quantizer. 1 Considering a recent survey of state-of-the art ΣΔ ADCs, the region corresponding to a resolution higher than 14-b is massively populated by SC-ΣΔ modulators, while CT modulators approach the state-of-the art frontiers at lower resolutions.…”

Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption

“…In this section, we analyze some class AB fully differential OTAs presented in the literature, with a focus on topologies that have been implemented in recent years in low voltage short-channel technologies [18][19][20][21][22]. Ref.…”

Thermal noise analysis of switched‐capacitor integrators with correlated double sampling

“…The switched-capacitor (SC) technique is popularly used in analog or mixed-signal CMOS integrated circuits [1,2]. To suppress the effects of DC offset and the flicker noise of operational amplifiers (opamps) in SC circuits, the correlated double-sampling (CDS) technique is widely adopted.…”