Design‐oriented model for power‐driven design optimization of SC‐ΣΔ modulators

Abstract

A behavioral model for switched-capacitors sigma-delta modulators, suitable for power-driven design, is presented. Because of the oversampling behavior of this kind of analog-to-digital converters, transistor-level simulations are extremely time consuming. Thus, accurate behavioral models are mandatory in the preliminary design steps to cut the development time. However, when the power consumption of the modulator is pushed down to the absolute minimum level, second-order effects affecting the settling behavior of the switched-capacitor integrator must be taken into account. Furthermore, by means of an accurate noise model, based on a second-order transfer function of the amplifier, a global power minimization is achieved, and the optimum partitioning between the switch and op-amp noise is obtained. In spite of the improved accuracy, the proposed model requires only a few parameters of the amplifier in the integrator. This allows to easily link the model to an external set of circuit equations, to be derived for the specific amplifier used in the modulator. The model was used in the design of a third-order modulator in an STM 90-nm technology. The silicon samples exhibit an effective resolution of 15.2-b with a 500-Hz output rate, an oversampling ratio of 500, and a Schreier figure-of-merit of 162 dB, with a 38-W power consumption at 1.2-V supply.

Energy Efficiency in Slew-Rate Enhanced Single-Stage OTAs for Switched-Capacitor Applications

“…More specifically, it derives from the phase-margin degradation of the RFC topology due to the non-dominant pole determined by the current mirrors Mm1-Mm2 and Mm3-Mm4 (see Figure 3a). In such condition the single-pole OTA approximation used in Equation ( 1) is not accurate, reinforcing the need for more refined models to abstract circuit behaviour including the presence of non-dominant singularities in the OTA frequency response [8].…”

“…The settling behaviour of Switched-Capacitor (SC) stages, as the one depicted in Figure 1a, has been conveniently described by a simplified model [1][2][3][4][5][6][7][8]. This model breaks down the charge-transfer operation in a SC stage, whether a SC amplifier or a SC integrator, into two phases, corresponding to the idealized operating regions of the OTA: slew rate and linear regions.…”

Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions

“…Therefore, as one can infer, due to the many target specifications, the many design variables and constraints, and the sparse ranges of the search spaces of every performance of an IC, then analog design automation tools are required to optimize CMOS ICs. On the one hand, some works are focused on the generation of behavioral models [10], which are used in the automatic design of amplifiers [11], and for the optimization of complex designs like switched-capacitors sigma-delta modulators [12]. However, optimization by using behavioral models barely found optimal solutions because they do not consider real models of the MOS transistors.…”