A Device Design for 5 nm Logic FinFET Technology

Ding, Yu; Luo, Xin; Shang, Enming; Hu, Shaojian; Chen, Shoumian; Zhao, Yuhang

doi:10.1109/cstic49141.2020.9282491

Cited by 5 publications

(2 citation statements)

References 3 publications

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“…The threshold voltage decreases with the reduction of channel length, but the opposite is observed for the subthreshold slope (SS) because the FinFET with 5 nm node technology is more immune to short Channel Effect (SCE) [6][19]. We note that the result obtain in this simulation for the performance ratio ION/IOFF is higher than that calculated by Yu Ding et al [5] and the result of threshold voltage obtained is better than that calculated by Vinay Vashishtha [4].…”

Section: Fig 5 Transfer Characteristics Of N Finfet 5nmmentioning

confidence: 54%

Impact of the geometric parameters on the performance of silicon TG SOI N FinFET 5nm

lazzaz

Bousbahi²,

Ghamnia

2022

Preprint

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Semiconductor device dimensions have been downsized to nanoscale dimensions to upgrade the driving capacity and increasing speed. At the lower technology node, the performance of conventional CMOS circuits degrades because of the short channel effects (SCEs). the researchers expect to identify new solutions for different design issues as a result, the FinFET device has been introduced as an alternative to MOSFET for advanced scalability which allows the use of multi gates in order to dissipate lower power. This paper presents an analysis of TG N SOI (Semiconductor On insulator) FinFET 5 nm using Hafnium Dioxide and the Non-Equilibrium Green Function (NEGF) formalism to study the quantum effect. The different parameters such as leakage current, the ON current, the performance ratio ION/IOFF which are calculated and optimized. The aim and the novelty of this simulation is to present novel geometric parameters that improve the performance of the device, and hence to have optimized CMOS circuits.

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Section: Fig 5 Transfer Characteristics Of N Finfet 5nmmentioning

confidence: 54%

Impact of the geometric parameters on the performance of silicon TG SOI N FinFET 5nm

lazzaz

Bousbahi²,

Ghamnia

2022

Preprint

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“…As an alternative to planar metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FinFETs), which utilize a three-dimensional architecture with the gate wrapping around vertical fins on top and sides, have been developed and commercialized in 22 nm CMOS technology [1][2][3]. During the past decades, FinFET technology has been successfully applied to 5 nm and even 3 nm technology nodes through higher aspect ratio and layout optimization [4][5][6][7][8]. However, the scaling of Fin-FETs has also encountered fabrication-and performance-related obstacles due to fundamental physical limitations and difficulties in developing the required process.…”

Section: Introductionmentioning

confidence: 99%

Compact Modeling of Advanced Gate-All-Around Nanosheet FETs Using Artificial Neural Network

Zhao,

Xu,

Tang

et al. 2024

Micromachines

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As the architecture of logic devices is evolving towards gate-all-around (GAA) structure, research efforts on advanced transistors are increasingly desired. In order to rapidly perform accurate compact modeling for these ultra-scaled transistors with the capability to cover dimensional variations, neural networks are considered. In this paper, a compact model generation methodology based on artificial neural network (ANN) is developed for GAA nanosheet FETs (NSFETs) at advanced technology nodes. The DC and AC characteristics of GAA NSFETs with various physical gate lengths (Lg), nanosheet widths (Wsh) and thicknesses (Tsh), as well as different gate voltages (Vgs) and drain voltages (Vds) are obtained through TCAD simulations. Subsequently, a high-precision ANN model architecture is evaluated. A systematical study on the impacts of ANN size, activation function, learning rate, and epoch (the times of complete pass through the entire training dataset) on the accuracy of ANN models is conducted, and a shallow neural network configuration for generating optimal ANN models is proposed. The results clearly show that the optimized ANN model can reproduce the DC and AC characteristics of NSFETs very accurately with a fitting error (MSE) of 0.01.

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Recent Trends in Novel Semiconductor Devices

Pandey

2022

Silicon

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A Device Design for 5 nm Logic FinFET Technology

Cited by 5 publications

References 3 publications

Impact of the geometric parameters on the performance of silicon TG SOI N FinFET 5nm

Impact of the geometric parameters on the performance of silicon TG SOI N FinFET 5nm

Compact Modeling of Advanced Gate-All-Around Nanosheet FETs Using Artificial Neural Network

Recent Trends in Novel Semiconductor Devices

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